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Overview
The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this particular datasheet, the PHY has been configured to support HMC-32G-VSR specifically, but the PHY itself can be configured to support a wide range of HS SERDES protocols through changes to the PCS layer and register settings.
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.
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Tech Specs
Part Number | Inno SerDes PHY & Controller |
Short Description | 32G Multi-SerDes PHY |
Provider | |
Maturity | Silicon proven and validated |
Foundry | SMIC, TSMC, AMS, Samsung |
Geometry nm | 4, 5, 6, 7, 8 |
Target Process Node | TSMC 5/6/7, SMIC 7, Samsung 8/7/5/4nm |