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100 "Wireline Communication" Solutions

1
112G LR Multi-protocol SerDes PHY
An ADC-based long-reach (LR) 112G SerDes PHY solution providing leading-edge performance and power efficiency for next-generation networking and hyperscale data center applications.

2
CXL (Compute Express Link) Dual Mode Controller
Highly Configurable, Technology Independent, System Validated.

3
Mobiveil RapidIO Controller (GRIO)
Generic RapidIO (GRIO) controller is a highly flexible and configurable IP to provide RapidIO interface on one side and a generic interface on the system side.

4
NVMStor
NVMStor platform offers high performance and low power SSD solution with its UNH certified NVMe controller IP.

5
NVMStor-Ultra
NVMStor-Ultra platform offers high performance and low power SSD solution with its UNH certified NVMe controller IP (UNEX). Based on Xilinx's high performance ZYNQ Ultrascale plus FPGA,

6
XpressLINK - Controller IP for CXL
XpressLINK™ is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation.

7
Ethernet IP Subsystem
Comprehensive portfolio of fully configurable multi-channel, multi-rate Ethernet MAC, PCS and FEC IP. Support for the OIF FlexE in addition to IEEE 802.3 standard for data center applications.

8
Ethernet Packet Processor

Gigabit Ethernet has become the leading choice for routing data around today's cars as they become increasingly complex automotive computing platforms. To meet the needs for flexible, high-spee...


9
16G Programmable SerDes PHY
Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provide optimization of power, performance and area to meet the growing needs...

10
C2C Chip to Chip Link Inter-chip Connectivity IP
The purpose of inter-chip connectivity IP is to connect two different chips together to share computing resources, limit chip-to-chip latency, or maintain the highest possible chip-to-chip bandwidth. ...

11
Ethernet Subsystem 10G/25G
Comcores Ethernet Subsystem is a silicon-agnostic, easy-to-use integration of 10G/25G Ethernet MAC and PCS for Time-Aware Applications. The Subsystem comes in different variations and can be delivered...

12
FlexLLI MIPI Low Latency Interface (MIPI LLI) Digital Controller Interchip Connectivity IP
Arteris FlexLLI digital controller IP is the industry s first and only silicon-proven implementation of the MIPI Low Level Interface (LLI) specification. Arteris FlexLLI digital controller IP can con...

13
FlexNoC Network on Chip SoC Interconnect IP
FlexNoC is the ideal interconnect for SoC designs requiring higher performance with minimum area and power. Its flexible architecture makes it the right solution for interconnects with both low latency requirements and high throughput needs. FlexNoC provides support for the additional features that today SoCs require, such as clock domain conversion, width conversion, security, and multi-protocol support. The product supports the AMBA (APB, AHB, AXI) protocols and OCP and can easily be extended to support proprietary protocols.

14
FlexNoC Resilience Package
The Arteris FlexNoC Resilience Package provides hardware-based data protection for increased SoC reliability and functional safety.

15
FlexNoC Resilience Package IP
The Arteris FlexNoC Resilience Package is a complementary product to Arteris FlexNoC fabric IP. It implements hardware resilience features essential for systems-on-chip (SoCs) targeted for mission-cri...

16
Gigabit Ethernet PHY IP
Faraday has developed the Ethernet PHY solutions for its ASIC SoC designs and IP licensing from UMC 0.13um to 28nm process.

17
Ncore Cache Coherent Interconnect IP
For scalable and area-efficient heterogeneous cache coherent systems.

18
PIANO 2.0 Automated Interconnect Timing Closure Technology
PIANO 2.0 solves back-end timing problems with technology that works earlier in the SoC design flow, thereby reducing schedule risk.

19
10G PHY for PCIe 2.0 in TSMC (7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


20
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


21
10G PHY for PCIe 3.0 in TSMC (16nm, 12nm, 10nm, 7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


22
10G TCP & UDP Offload Engines, Ultra Low latency
INT 25012 is the only SOC IP Core that implements a full 10G bit TCP and UDP Stack inHand crafted, Ultra-High Performance, Innovative, Flexible and Scalable architecture which can also be easily custo...

23
10G TCP+UDP Offload Engine+PCIe Ultra-Low Latency
INT 25012 is the only SOC IP Core that implements a full 10G bit TCP and UDP Stack in Handcrafted, Ultra-High Performance, Innovative, Flexible and Scalable architecture which can also be easily custo...

24
12G PHY

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


25
12G PHY in TSMC (28nm, 16nm, 12nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


26
12G PHY in UMC (28nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


27
16G PHY

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


28
16G PHY in TSMC (28nm, 16nm, 12nm)

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


29
200/400 Gigabit Ethernet MAC and PCS Solution
Traffic demand in the carrier backbone continues to grow rapidly, driven by a number of popular applications such as IPTV, video-on-demand services, remote storage, mobile broadband services, and VPN ...

30
25G PHY

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


31
25G PHY in TSMC (16nm, 12nm, 7nm)

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


32
32G PHY in TSMC (7nm)

The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY...


33
40G TCP/UDP Offload Engine
INT 40011 is the only SOC IP Core that implements a full 40G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance, Innovative, Flexible and Scalable architecture which can also be easi...

34
50G//25G TCP/UDP Offload Engine
INT 25011 is the only SOC IP Core that implements a full 25G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance, Innovative, Flexible and Scalable architecture which can also be easi...

35
56G Ethernet PHY in TSMC (16nm, 7nm)

The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leadingedge design, analysis, simulation, and measureme...


36
6G PHY in TSMC (16nm)

The multi-lane DesignWare Multi-Protocol 6G PHY IP is part of Synopsys' highperformance multi-rate transceiver portfolio, meeting the growing needs for small area, low bill of materials (BOM) c...


37
Configurable Ethernet controllers, compliant with the IEEE and consortium specifications for a range of applications

DesignWare® Ethernet IP solutions consist of configurable controllers, PHYs supporting speeds of up to 400G, verification IP, IP Prototyping Kits, Software Development Kits, and Interface IP Su...


38
DesignWare 200G/400G Ethernet PCS IP
The DesignWare 200/400G and 800G Ethernet MAC and PCS IP solutions enable a host to transmit and receive data over Ethernet. The PCS IP is optimized for low latency and supports multi-rates for up to ...

39
Dual ODU0 Mapper / Demapper
The Xelic Optical Transport Network (OTN) Dual ODU0 Mapper/Demapper performs mapping/demapping of two 1000 BASE-X Gigabit Ethernet signals encapsulated in transparent GFP frames to/from a single OTN ODU1 frame format or two independent ODU0 data streams.

40
Dual Port Gigabit Ethernet Transcode Application
The Xelic XA304 Application supports the mapping of dual Transcoded Gigabit Ethernet signals into ODU0 frames and ODTU01 multiplexing for ODU1/OTU1 frame rate transport.

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