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93 "Wireline Communication" IP

1
10G PHY for PCIe 2.0 in TSMC (7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


2
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


3
10G PHY for PCIe 3.0 in TSMC (16nm, 12nm, 10nm, 7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


4
12G PHY

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


5
12G PHY in TSMC (28nm, 16nm, 12nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


6
12G PHY in UMC (28nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


7
16G PHY

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


8
16G PHY in TSMC (28nm, 16nm, 12nm)

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


9
25G PHY

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


10
25G PHY in TSMC (16nm, 12nm, 7nm)

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


11
32G PHY in TSMC (7nm)

The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY...


12
56G Ethernet PHY in TSMC (16nm, 7nm)

The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leadingedge design, analysis, simulation, and measureme...


13
6G PHY in TSMC (16nm)

The multi-lane DesignWare Multi-Protocol 6G PHY IP is part of Synopsys' highperformance multi-rate transceiver portfolio, meeting the growing needs for small area, low bill of materials (BOM) c...


14
Configurable Ethernet controllers, compliant with the IEEE and consortium specifications for a range of applications

DesignWare® Ethernet IP solutions consist of configurable controllers, PHYs supporting speeds of up to 400G, verification IP, IP Prototyping Kits, Software Development Kits, and Interface IP Su...


15
DesignWare 200G/400G Ethernet PCS IP
The DesignWare 200/400G and 800G Ethernet MAC and PCS IP solutions enable a host to transmit and receive data over Ethernet. The PCS IP is optimized for low latency and supports multi-rates for up to ...

16
1G to 200G High Speed Channelized Ethernet Controller MAC/PCS/FEC
200G aggregate bandwidth channelized solution for up to four Ethernet channels

17
200G/400G High Speed Ethernet Controller MAC/PCS/FEC
200G/400G bandwidth solution for one Ethernet channel

18
400G/800G High Speed Ethernet Controller MAC/PCS/FEC
800G/400G bandwidth solution for one Ethernet channel

19
400G/800G High Speed Ethernet Controller PCS/FEC
Up to 800G bandwidth solution for one Ethernet channel

20
Ethernet 10G MAC
The IP for 10 Gigabit Ethernet MAC is designed for use in 10 Gigabit Ethernet applications. For ease of integration into a wide range of applications, this IP is integrated with a 64-bit FIFO user in...

21
Ethernet 10G MAC with DMA
The IP for 10 Gigabit Ethernet MAC is designed for use in 10 Gigabit Ethernet applications. The XGM_GXL offers two mutually exclusive connections to the host interface or system bus. A 64 or 128 bit ...

22
Ethernet XAUI PCS
Integrates MAC IP to a broad range of PHY and SerDes IP

23
NVMStor
NVMStor platform offers high performance and low power SSD solution with its UNH certified NVMe controller IP.

24
NVMStor-Ultra
NVMStor-Ultra platform offers high performance and low power SSD solution with its UNH certified NVMe controller IP (UNEX). Based on Xilinx's high performance ZYNQ Ultrascale plus FPGA,

25
USXGMII Ethernet PCS (PCSR_X)
The Cadence USXGMII PCS (PCSR_X) IP provides the logic required to integrate a USXGMII, 5GBASE-R, or 10GBASE-R PCS into any system on chip (SoC).

26
16G Programmable SerDes PHY
Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provide optimization of power, performance and area to meet the growing needs...

27
Gigabit Ethernet PHY IP
Faraday has developed the Ethernet PHY solutions for its ASIC SoC designs and IP licensing from UMC 0.13um to 28nm process.

28
ITU 25G PON LDPC Encoder and Decoder
The ITU-T G.9804.2 Recommendation defines the common transmission convergence (ComTC) layer for Higher Speed Passive Optical Networks. As part of the Forward Error Correction (FEC) in the ComTC layer....

29
Ethernet Subsystem 10G/25G
Comcores Ethernet Subsystem is a silicon-agnostic, easy-to-use integration of 10G/25G Ethernet MAC and PCS for Time-Aware Applications. The Subsystem comes in different variations and can be delivered...

30
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY

31
Apodis - OTN Processors
The Apodis family of ITU-T compliant Optical Transport Network (OTN) processors offer termination, processing, framing, multiplexing, demultiplexing and switching of OTN signals, in addition to client...

32
Comira Ethernet IP Solution
CoMira's multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully configurable and programmable to support "any rate on any channel" (400G/200G/100G/50G/25G/10G/1G).

33
Ethernet 10/100 PHY
The KA13ETHB33 is a single-port PHY with an MII (Media Independent Interface). It implements all 10/100M Ethernet Physical- layer functions including the Physical Coding Sub-layer (PCS), Physical Medi...

34
Fabri, a novel Network Fabric
The idea of Fabri3 is to dis-aggregate the network from the servers and connect each server via PCIe cables to the Fabri3. Up to 64 servers can be attached to Fabri3 u...

35
Gemini - OTN IP Cores
The Gemini product family of OTN processors IP cores are intended and optimized for Premium Services and Access applications. Gemini client ports support one or two Ethernet/SDH signals and multiplexe...

36
Gen-Z Physical Layer for 802.3
The IPC-GZ196A-ZM Gen-Z Physical Layer for 802.3 is an IP Core that allows companies to attach a Gen-Z core to an 802.3 Phy.

37
Orion MFH IP Cores
The Orion family of Intellectual Property (IP) Cores are intended and optimized for 4G Mobile Front-Haul (MFH) networks. Orion IP Cores transport the following CPRI signal options according to ITU-T, ...

38
Remote Evaluation Systems
EXTOLL has created a disruptive interconnect technology with the TOURMALET ASIC being its currently available manifestation. The EXTOLL technology is highly performant and offers a variety of features...

39
Scorpion - OSU IP cores
The Scorpion OTN/OSU (Optical Service Units) processors IP cores product family are a member of Tera-Pass product family for access applications. Scorpion OSU processors are offered as integrated s...

40
Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC
SP-10_100_ETHERNET-T12FFC is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream to and from a Media Access Control (MAC) and to and...

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