When : September 16th, 2025
Where: COEX Conference Rooms 317 and 318 3rd Floor, COEX, 513 Yeongdong-daero, Gangnam-gu, Seoul, 06164, South Korea
Join D&R IP SoC South Korea 25 !! A worldwide connected Event !!
Co-organized with:

A worldwide connected Event !!
D&R IP-SoC South Korea 2025 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems.
IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry.
IP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view, Electronic systems leaders may identify disruptive innovation leading to new market segment growth.
Any question? Please contact us
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9.00 am
Welcome Session
Chairperson: Jeong-Hoi Kim, KSIA
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Opening talk from KSIA Vice Chairman
Jeong-Hoi Kim ViceChair KSIA
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Welcome to the IP SoC community
Gabrièle Saucier CEO Design And Reuse
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9.20 am
Artificial Intelligence - Part 1
Chairperson: Byoung Du Yu
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Accelerating vector databases in the data-driven AI era
Se-Hyun Yang CTO Dnotitia
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Scalable, Flexible Edge AI accelerator - Silicon-Proven IP for Smart-X and Robotics
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Changsoo Kim AiM Future, Inc.
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Neural Video Processor IP the AI Engine for Video
Yujing Wei VP Sales & Country Manager APAC Allegro DVT
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Unlocking Generative AI at the Edge: How LPDDR enables Scalable & Efficient Intelligence
As generative AI continues to redefine the boundaries of creativity and automation, its true value is realized when inference is optimized for real-world deploymentespecially at the edge. This presentation explores how inference serves as the c ritical enabler for delivering generative AI experiences that are responsive, efficient, and scalable. We will examine how LPDDR memory technologies, with their unique balance of high bandwidth, low latency, and cost efficiency, are ideally suited for edge AI applicationsfrom smart cameras and industrial sensors to autonomous systems. The session will highlight architectural considerations, performance benchmarks, and deployment case studies that demonstrate how LPDDR empowers edge inference chips to meet the demands of generative AI workloads. ...
Suk Keun Youn Director, Silicon IP Rambus, Inc.
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Break
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11.00 am
Artificial Intelligence - Part 2
Chairperson: Byoung Du Yu
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The Next Evolution of AI: Edge First!
Seung-Kee Kim Korea & SEA Sales manager Ceva, Inc.
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High-performance LPDDR IP Solution for Automotive AI
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Hweihn Chung EVP OPENEDGES Technology, Inc.
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Advanced Automotive AI/ML Networks
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Seyoung (Sean) Park - Applications Engineer Quadric
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Image compression for AI and machine learning
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Jungmin Joo Country Manager intoPIX
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1.30 pm
Chiplets and Network on Chip
Chairperson: Ook Kim, 4lynx
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How UCIe is Progressing to enable Chiplets
The concept of mixing and matching chiplets in a single package is still under evaluation. UCIe has paved the way for turning this vision into reality by standardizing die-to-die interconnects. However, further advancement is necessary to ensure succ ess, particularly in meeting the requirements of AI chips and new applications such as cHBM. This presentation highlights the various requirements for UCIe IP operating up to 64Gbps, providing proof points to illustrate the different UCIe variants in standard and advanced packaging and advanced process technologies. ...
Hyoung-Bae Choi Sr. Director Synopsys, Inc.
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Updated Methodology to Generate Optimal NoCs in 2025
AI has shifted SoC design focus from compute to data movement. The solution? Network-on-Chip (NoC). Yet designing an optimal NoC is time-consuming. This presentation explores advanced tools that dramatically accelerate NoC creation helping arc hitects deliver high-performance, efficient interconnects in a fraction of the time. ...
John Min VP of Customer Success Arteris IP
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Shaping the Future of High-Performance Chips: DRAM, SerDes, and Chiplet IP Innovations
Mason Li VP, Director (ASIA ex-China) Innosilicon
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Break
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3.00 pm
Analog and Memory IP
Chairperson: Gabriele Saucier, D&R
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Analog IP Solution for SAMSUNG Foundry
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Myeonglyong Ko R&D Center Director LeoLSI
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Advancing Power Telemetry
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David Steer VP Wordwide Sales Movellus, Inc.
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SLM PVT Monitors IP Overview
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Sehee Han Sales Account Management, Principal Synopsys, Inc.
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Building Tomorrow Today: Enabling the Future of HPC With 4lynx's High-Performance PVT Monitoring Solutions
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Ook Kim CEO 4lynx
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1.30 pm
Security Solutions
Chairperson: David Park, Quadric
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Protecting Data in Motion with MACsec
As companies adopt high-performance computing, AI workloads, and cloud-edge architectures, protecting data in motion within and across networks is a growing imperative. This presentation will examine a critical technology that addresses this challeng e: MACsec (Media Access Control Security). The presentation will explore how MACsec secures Layer 2 Ethernet communications against eavesdropping, replay, and man-in-the-middle threats. In addition, given how Ethernet technology continues to scale and proliferate across the application space, current and future implementations of MACsec from the data center to the automotive market will be discussed. ...
Suk Keun Youn Director, Silicon IP Rambus, Inc.
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Securing the Future: Challenges and Solutions in Post-Quantum Cryptography
This presentation introduces Post-Quantum Cryptography (PQC), its growing importance in the face of quantum threats, and the global standardization efforts underway. It also highlights Secure-ICs unique role in securing the cryptographic value chain from IP integration to device certification for a quantum-resilient future. ...
Ahmed BOUGRIANE Field Application Engineer Secure-IC
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Integrated, Scalable, Proven: Why Security IP Outclasses Custom Approaches
Using dedicated, programmable Security IP is a stronger choice than relying on custom-built or general-purpose security solutions. Backed by over 30 years of experience in end-to-end security, Kudelski Labs explains why integrated, scalable and prove n IP delivers stronger protection, faster development, and easier certification, while reducing complexity and long-term risk. ...
Lamyae Lahlou Product Line Manager Kudelski Labs
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Error-Redundant Implementation of Commercial IP Cores: A Practical Example
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Dongwan Kang Korea Sales Executive SmartDV Technologies
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Securing Chips In-Field: Why silicon lifecycle management matters
Shahram Mossayebi CEO Crypto Quantique
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Break
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3.30 pm
Video IP
Chairperson: Dagmara Zielinska, D&R
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CFrame60 - Frame Buffer Compression for bandwidth reduction using lossy/lossless techniques in video processing
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Junghyun Kwon CTO Chips&Media, Inc.
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AV1 Video Encoder IP for Data Center-Grade Quality
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Mickey Jeon CEO BLUEDOT
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Efficient Lossless Compression: Trade-offs, Performance of Algorithms and IP Cores
As data volumes surge across cloud, AI, automotive, and edge systems, efficient lossless compression has become essential for meeting performance, latency, and bandwidth constraints. This presentation explores the trade-offs and strengths of the indu stry's leading compression algorithms–GZIP, LZ4, Snappy, and Zstd–highlighting how hardware-accelerated implementations can overcome the limitations of software-based solutions in demanding, real-time environments. You'll gain insights into latency vs. compression ratio vs. resource trade-offs, integration strategies for FPGAs and ASICs, and real-world applications like high-speed networking and automotive data logging. Discover how to boost your system's efficiency and unlock next-level performance through compression IPs tailored for modern hardware. ...
Evan Price CAST
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