When : April 23rd, 2026
Where: Hyatt Regency Santa Clara
5101 Great America Parkway, Santa Clara, CA
Join D&R IP SoC Silicon Valley 26 !! A worldwide connected Event !!
A worldwide connected Event !!
D&R IP-SoC Silicon Valley 2026 is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems.
IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry.
IP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view, Electronic systems leaders may identify disruptive innovation leading to new market segment growth.
Any question? Please contact us
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⮞ Tentative list of first Contributions, more to come...
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9.00 am
Welcome Session
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Semiconductor IP in the AI era
Gabrièle Saucier
CEO
Design And Reuse
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with Dagmara Zielinska
Design And Reuse
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Why Now Is A Critical Moment To Think About On-Chip Smarts For Power and Thermal Efficiency
Mahesh Tirupattur
Executive Vice President
Analog Bits Inc.
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9.40 am
AI Solutions
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The On-Device AI Revolution: Processor Strategies for the LLM World
As large language models (LLMs) and small language models (SLMs) move from the cloud to edge devices, semiconductor architects face an entirely new set of design constraints. Running generative AI workloads on-device requires careful balancing of sto rage capacity, memory bandwidth, compute density, and power efficiency — all within tight silicon area and cost budgets. In this session, Steve Roddy, Chief Marketing Officer at Quadric Inc., will explore the fundamental storage, bandwidth, and compute tradeoffs that shape modern AI processor design. The talk will examine scalable and programmable silicon strategies for enabling LLM and SLM inference directly on-device, without reliance on cloud connectiv  ... 
Steve Roddy
CEO
Quadric
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Disrupting Edge AI Silicon Solutions: 90% cost/ power consumption reduction for the next generation Edge AI Chip
The current era of Edge AI is constrained by traditional silicon architectures that rely on instruction-driven "Control Flow." In these conventional systems, a significant portion of energy and silicon area is dedicated to managing software instructi ons rather than performing the actual AI math. This "instruction tax" results in high power consumption and latency, creating a bottleneck for deploying sophisticated Large Language Models (LLMs) on resource-constrained edge devices. DeepMentor introduces a paradigm shift through a specialized architecture that transitions from software-dependent processing to mathematically hardened, pure dataflow circuits. By physically embedding the fundamental primitives of modern AI models into the silicon, this approach eliminates the overhead associated with traditional instruction fetching and decoding. The result is a breakthrough in efficiency, achieving up to a 90% reduction in both power consumption and total silicon cost compared to standard NPU and GPU solutions. To maintain the agility required for the rapidly evolving AI landscape, this architecture utilizes a parametric design strategy that separates mathematical execution from sequence control. While the core arithmetic is hardened for maximum speed, the data paths remain reconfigurable through a lightweight runtime. This allow the hardware to dynamically support a diverse range of model structures and layer counts without redesigning the circuit, providing a "best-of-both-worlds" solution that combines ASIC-level performance with the flexibility to run the next generation of Edge AI models. ...
Richard Wu
General Manager
DeepMentor USA
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Scalable, Flexible Edge AI accelerator - Silicon-Proven, and Market-Proven IP for Edge AI applications
Changsoo Kim
Founder & CEO
AiM Future, Inc.
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Break
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11.00 am
AI Solutions - 2
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Enabling Efficient Edge AI Inferencing Through Ecosystem Collaboration
Nidish Kamath
Director of Product Management, Silicon IP
Rambus, Inc.
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Addressing Physical AI application Challenges with Standards-Based IP
The design of PVT monitoring IP must undergo a major rethink to stay ahead of the curve and adapt to the advent of the GAA transistor. The current lack of thick oxide MOSFET device makes BJT based designs impractical since they operate at higher volt ages around 1.2v. In some processes BJT is eliminated resulting in the need to use MOSFET or thermal resistor as a sensing element. This shift in sensing technology is pushing us away from AMS architecture for PVT IP. Digitally Assisted Analog (DAA) architecture has the benefit of not only a smaller area, lower power but also eliminate the need for shielding signal lines from the effect of noise/crosstalk needed for analog signals. Accuracy for DAA IP will be main trade-off compared to AMS IP but System on Chip (SoC) architects will be able to insert the IP closer to sense points due to smaller size, resulting in equivalent effective accuracy. ...
Hezi Saar
Synopsys, Inc.
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Legato-Logic: Time-Domain Neural Network Processor IP for Low Power and Low Latency AI Computation
Legato-Logic is a time-domain compute-in-memory IP based on a proprietary mixed signal technology. The architecture uses a weight-stationary array to compute deep neural network operations with very high parallelism and power efficiency. The fabricat ed mixed-signal technology achieves 50 fJ per 4-bit MAC operation for dense activity networks in 22 nm CMOS. It can operate near threshold supply voltage and save even more energy. The array size of 256X16 elements can perform 4096 4 bit-data by 4 bit-weight MAC operations per cycle and it occupies less than 1mm2 area. The array size is programable during the operation to optimize the power even further based on each CNN layer. The measured silicon results are less than 100 microwatts of power consumption for real-time person detection. ...
R Scott Hills
VP of Business Development
ANAFLASH Inc.
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Advanced mathematics foundation IP that accelerates AI accelerators
Most engineers know that AI accelerators are incredible mathematics machines, with the datacenter class of chips crunching quadrillions of mathematical operations (PetaFlops) every second. But they are still largely using mathematical algorithms and methods that were developed hundreds if not thousands of years ago. That is about to change, as there is now over a billion dollars of VC money invested in startups that are exploring non-IEEE mathematical methods to challenge the status quo on computational efficiency. Cassia.ai is making advanced mathematical methods available to IP users in the form of an IP foundation library for AI, that includes key functions that are 10X-20X accelerated compared to traditional math and 60%-90% fewer gates by using alternative mathematical methods in the digital domain. ...
Marc Greenberg
VP Product
Cassia.ai
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1.20 pm
Analog IP and Memory IP
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Analog IP and Memory IPs
Alphacore, Inc.
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Managing Power and Performance in the Age of AI
Pranshu Kalra
Analog Bits Inc.
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SLM PVT IP Tutorial in N2P GAA tech node using DAA architecture
The design of PVT monitoring IP must undergo a major rethink to stay ahead of the curve and adapt to the advent of the GAA transistor. The current lack of thick oxide MOSFET device makes BJT based designs impractical since they operate at higher volt ages around 1.2v. In some processes BJT is eliminated resulting in the need to use MOSFET or thermal resistor as a sensing element. This shift in sensing technology is pushing us away from AMS architecture for PVT IP. Digitally Assisted Analog (DAA) architecture have the benefit of not only a smaller area, lower power but also eliminate the need for shielding signal lines from the effect of noise/crosstalk needed for analog signals. Accuracy for DAA IP will be main trade-off compared to AMS IP but System on Chip (SoC) architects will be able to insert the IP closer to sense points due to smaller size, resulting in equivalent effective accuracy. ...
Rohan Bhatnagar
Product Management
Synopsys, Inc.
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Ternary and Tunnelling based approach for highly bit-dense and energy-efficient on-chip SRAM
KyungRok Kim
Ternell
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2.00 pm
Memory Subsystems
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The Widespread Use of LPDDR Memory Subsystems
Byul Choi
Head of Sales & Marketing
OPENEDGES Technology, Inc.
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LPDDR6/5X: The Future of Memory for AI, Security & Automotive
Farzad Zarrinfar
Senior Vice President of Sales & Marketing
Innosilicon
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AI Inference needs a mix-and-match memory strategy
AI inference spans diverse workloads, from low‑latency chat to long‑context reasoning and large‑scale recommendations—making single, monolithic accelerator and memory designs increasingly inefficient. This talk explains how inf erence naturally splits into prefill and decode stages with fundamentally different bottlenecks: prefill is compute‑bound, while decode is dominated by memory bandwidth and latency. By matching memory technologies to each stage, using cost‑efficient GDDR or LPDDR for prefill and reserving premium HBM for decode, with pooled memory for KV offload, operators can significantly reduce cost per token without sacrificing latency. The session outlines emerging disaggregated architectures for AI inference workloads. ...
Paul Karazuba
Vice President of Marketing, Silicon IP
Rambus, Inc.
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Memory controller solutions for Edge AI Applications
Ravi Thummarukudy
CEO
Mobiveil Inc.
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4.00 pm
Interface IP
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Display and High-Speed Interface IP Portfolio
Ook Kim
CEO
4lynx, Inc.
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Solving the AI Compute-to-I/O Gap with Scalable Interface IP
AI workloads are pushing compute scaling beyond what existing memory, die-to-die, and SerDes architectures can sustain, widening the compute-to-I/O gap and creating system-level bottlenecks. Closing this gap requires new architectures and advanced ch ip interfaces that can deliver higher bandwidth and lower latency with strict power and area efficiency. This session will discuss how different classes of AI workloadstraining, inference, and emerging distributed modelstranslate into growing demand for memory, D2D, and high-speed SerDes IP. It examines why power has become a primary design constraint at the rack and cluster level, and why latency sensitivity varies significantly across protocols and workloads. The session will also explore how rapidly evolving interface IP standards and one-generation-ahead readiness are critical to enabling the transition from general-purpose designs to purpose-built, compute-dense AI clusters. Attendees will gain an understanding of the bandwidth, power, latency, and area tradeoffs that interface IP must address to close the compute-to-I/O gap in next-generation AI systems, as well as insights into the key standards and technologies shaping interface IP. ...
Manmeet Walia
Synopsys, Inc.
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Marketing Our Interface IP and MIPI DSI 2 TX and RX, CSI-2 TX and RX,A-Phy,UCie
We need to put stall in that exhibition.
TBD
Managing Director
MAXVY Technologies Pvt Ltd
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1.20 pm
RISC-V
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Bringing Tenstorrent's Ascalon RISC-V CPU IP to life via playable Doom
This presentation describes the incremental journey taking Tenstorrent’s Ascalon RISC-V CPU IP from initial RTL and emulation through a multi-phase hardware/software co-design process to achieve a playable DOOM demo on a HAPS prototyping platfor m, offering specific, hard-won lessons on toolchain integration, system bring-up, and performance optimization for RISC-V adoption. ...
Rae Parnmukh
Director, IP Product Operations
Tenstorrent
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The New RISC-V Spectrum of AI Compute
As SoC architectures evolve under pressure from AI workloads, power constraints, and the need for long-term platform differentiation, organizations are rethinking how compute platforms scale across the entire spectrum from hyperscale datacenters to h ighly efficient edge devices. This presentation will introduce new industry data on RISC-V and explore how companies across regions and industries are developing modern SoC platforms, illustrated by real-world examples from Aion Silicon's work spanning datacenter AI accelerators and host CPUs to edge AI systems, embedded processors, and microcontrollers now entering volume production. ...
Oliver Jones
CEO
Aion Silicon
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1.40 pm
Multi Media
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Scaling Class-D to Advanced Nodes: A New Standard for Embedded Audio
While the efficiency advantage of Class-D amplification over Class-AB is well recognized in Audio, the true breakthrough emerges when it is implemented in advanced process nodes. These technologies enable smaller silicon area, lower power consumption , improved device matching, and deeper SoC integration. This session highlights how such integration empowers engineers to design ultra-compact, battery-optimized hearable and wearable devices, while providing marketing teams with a strong differentiation story built on clear technology leadership. ...
Etienne Faucher
Productline Portfolio Manager - Audio
Dolphin Semiconductor
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Multimedia AI application in edge device – evolution and how to prepare
Andy Lee
Vice president, US marketing
Chips&Media, Inc.
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2.20 pm
Security Solution
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Architecting a Flexible Root of Trust Across SoC Security Frameworks with PUFrt
Modern SoCs span diverse security frameworksfrom open-source platforms such as Caliptra to PSA-like TrustZone architectures and custom security subsystems. This session presents PUFrt as a silicon trust anchor that integrates consistently across the se models while aligning with post-quantum cryptographic capabilities within each architectural path. ...
Matthew Yu
Marketing Manager
eMemory Technology Inc.
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Hardware-Software Co-Design and Side-Channel Resilience Challenges in Post-Quantum Cryptography IP
he transition to post-quantum cryptography (PQC) is a critical evolution in securing future silicon platforms, yet it introduces unique hardware and software co-design challenges at the IP level. PQC algorithms impose demanding requirements on perfor mance, memory footprint, and determinism, making seamless co-design essential to meet area, power, and throughput targets without compromising security. This presentation will explore key challenges in PQC IP integration, including algorithm-architecture mapping across hardware and software boundaries, cross-layer optimization in constrained systems, and synchronization between cryptographic kernels and host software frameworks. We will highlight real-world integration complexities encountered during iterative design updates and discuss best practices for maintaining architectural flexibility while preserving implementation efficiency. In addition, side-channel vulnerabilities—especially in power, electromagnetic, and timing domains—remain a significant security risk for PQC implementations. We will examine practical side-channel attack vectors, mitigation strategies, and tradeoffs in countermeasure design that impact performance, verification complexity, and silicon cost. Attendees will gain actionable insights into prioritizing design choices, evaluating co-design tradeoffs, and implementing robust side-channel protections in PQC IP and subsystem integration. ...
Reza Azarderakhsh
CEO
PQSecure Technologies
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with Patrick Manning
PQSecure Technologies
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Building Trust in the Age of AI and Quantum Threats
As AI adoption accelerates, quantum computing introduces new security risks that challenge existing trust models. This talk explores how post-quantum cryptography and hardware-based security can protect AI-driven systems across their lifecycle, ensur ing long-term resilience and trust. ...
TBD
Secure-IC SAS
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AI Beyond the Data Center: Securing Physical AI with Hardware-Rooted Trust
Dr Shahram Mossayebi
CEO
Crypto Quantique
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From Monolithic SoCs to Chiplets: A new Hardware Security Paradigm
Chiplet‑based architectures are transforming SoC design, but they also upend long‑standing security assumptions. By disaggregating a monolithic die into multiple, often multi‑vendor chiplets, the implicit silicon trust boundary disa ppears, expanding the attack surface to include chiplet substitution, weak‑chiplet compromise, and exposed die‑to‑die interconnects. This presentation explores why traditional SoC security models fail in chiplet systems and introduces a system‑level security paradigm based on distributed trust with centralized authority. ...
Berardino Carnevale
Senior Technical Marketing and Product Manager
Rambus, Inc.
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4.20 pm
Design and Validation Platform
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Future-Proofing SoCs: eFPGA IP Use Cases and Integration Made Predictable
Trey Peterson
Field Application Engineer
QuickLogic Corp.
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IP, subsystem and software validation
Ali Khan
co-CEO
Correva, Inc.
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