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You are here : Analog & Mixed Signal > Clock Synthesizer

Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm LP Process

Overview

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Tech Specs

Part Number	FXDCDL072HH0L
Short Description	Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm LP Process
Provider
Maturity	Pre-Silicon release
Foundry	UMC
Geometry nm	40
Target Process Node	UMC 40nm