Analog & Mixed Signal
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33 Silicon IP

1
32kHz Ultra-Fast-Lock IoT PLL
PLLTS7FFLBFLINT

2
Fractional-N Frequency Synthesizer PLL (3nm - 180nm)
PLLTS3FFFRAC

3
Ultra Low Area Frequency Synthesizer PLL (3nm - 90nm)
PLLTS7FFLAINT

4
Ultra-low Jitter Fractional-N Frequency Synthesizer PLL (5nm - 180nm)
PLLTS5FFLJFRAC

5
Ultra-Low Phase Noise Digital LC PLL
LCPLLTS7FFADE3

6
Very Low Area Fractional-N Frequency Synthesizer PLL
PLLTS3FEHBLAFRAC

7
Ultra-Low Phase Noise Delta Sigma Fractional-N LC PLL
PLLTS28HPMLC8

8
Ultra-Low-jitter Ring PLL
PLLTS40LPLJINT

9
Programmable Clock Generator
logiCLK

10
Nano power Real Time Clock (RTC) with 32kHz oscillator
SGCPMU_01_TSMC_CLN12FC

11
CMOP charge pump
350AMS_CP_01

12
ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX
ri_gf22fdx_clkgen_10m

13
ULP Clock-Generator - GLOBALFOUNDRIES 22FDX
ri_gf22fdx_clkgen

14
Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP
pPLL03F-GF12LPP

15
Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX
pPLL03F-GF22FDX

16
Fractional-N PLL for Performance Computing in Samsung 14LPP
pPLL03F-S14LPP

17
Fractional-N PLL for Performance Computing in Samsung 8LPP
pPLL03F-S8LPP

18
Fractional-N PLL for Performance Computing in TMSC 16FFC
pPLL03F-T16

19
Fractional-N PLL for Performance Computing in TSMC N5/N4
pPLL03F-TN4

20
Fractional-N PLL for Performance Computing in TSMC N6/N7
pPLL03F-TN7

21
Fractional-N PLL for Performance Computing in UMC40LP
pPLL03F-UMC40LP

22
Fractional-N PLLs for Performance Computing
pPLL03F Family

23
Integer-N-PLL-based HF Frequency Synthesizer and Clock Generator with integrated Loop Filter and VCO
TS_FS_9M70_X8

24
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process
FXPLL360HF0G

25
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
FXPLL360HH6L

26
Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process.
FXPLL610HF0F

27
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process.
FXDCDL344HH0L

28
Input 5M-35MHz, output 5M-35MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF ; UMC 40nm LP Process
FXDCDL072HH0L

29
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
FXDLL344HH0L

30
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process
FXOSC008HF0F

31
IP name: FXS2D101HH0L Area: 300um*300um
FXS2D101HH0L

32
NO External-R ,frequency 30K~60K ,RC Oscillator . Power:2.0V~3.6V; UMC 55nm EFLASH process. _x000D_
FXOSC045HF0F

33
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process
FXOSC003HF0L

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