SEARCH IP
- - Categories
  - RISC-V
  - Embedded Processing
  - 5G, 3GPP LTE IP
  - IoT IP
  - Artificial Intelligence IP
  - Automotive IP
  - Space and Avionics
  - Security IP
  - Audio & Video IP
- - Design Platforms
  - Monitoring and Verification
  - SoC Design Services
  - Find your best SoC design partner
Partner Videos
D&R Events
- - IP-SoC Days 2024
  - IP-SoC Days 2023
  - IP-SoC Days 2022
  - IP-SoC Days 2021
  - IP-SoC Days 2020
  - IP-SoC 2023
  - IP-SoC 2022
  - IP-SoC 2021
  - IP-SoC 2020
NEWS

You are here : Analog & Mixed Signal > Clock Synthesizer

Fractional-N PLL for Performance Computing in UMC40LP

Overview

Perceptia’s DeepSub™ pPLL03F is a PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requirements at frequencies up to 4GHz. It is suitable as a clock source for performance computing blocks and ADCs/DACs with moderate SNR requirements.

Please sign in to view full IP description :

Tech Specs

Part Number	pPLL03F-UMC40LP
Short Description	Fractional-N PLL for Performance Computing in UMC40LP
Provider
Maturity	In development
Foundry	UMC
Geometry nm	40, 65
Target Process Node	UMC 40LP. Portable to all CMOS processes 65nm and smaller.