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Overview
Perceptia’s DeepSub™ pPLL03F is a PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requirements at frequencies up to 4GHz. It is suitable as a clock source for high performance computing blocks and ADCs/DACs with moderate SNR requirements.
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Tech Specs
Part Number | pPLL03F-TN4 |
Short Description | Fractional-N PLL for Performance Computing in TSMC N5/N4 |
Provider | |
Maturity | In development |
Foundry | TSMC |
Geometry nm | 4, 5, 65 |
Target Process Node | TSMC N5/N4. Portable to all CMOS processes 65nm and smaller. |