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Overview
Perceptia’s DeepSub™ pPLL03F is a family of all digital PLLs featuring low-jitter and compact area suitable for clocking applications with critical timing requirements at frequencies up to 4GHz. It is suitable as a clock source for performance computing blocks and ADCs/DACs with moderate SNR requirements.
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Tech Specs
| Part Number | pPLL03F Family |
| Short Description | Fractional-N PLLs for Performance Computing |
| Provider | |
| Maturity | Silicon Proven |
| Geometry nm | 65 |
| Target Process Node | Portable to all CMOS processes 65nm and smaller. See specific product listings |