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Overview
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR4/DDR3/DDR3L SDRAM interfaces operating at up to 3200 Mbps. LPDDR4 support is available in the Synopsys LPDDR4 multiPHY. The Synopsys DDR4/3 PHY is ideal for systems that require high-speed DDR3/ 4 performance requiring high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 16 ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the Synopsys DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility
Optimized for high performance, low latency, low area, low power, and ease of integration, the Synopsys DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility
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Tech Specs
Part Number | dwc_ddr4_ddr3_phy_tsmc |
Short Description | DDR4/3 PHY in TSMC (12nm, 16nm, 7nm) |
Provider | |
Maturity | Available on request |
Foundry | TSMC |
Geometry nm | 8, 10, 11, 14 |
Target Process Node | 14nm, 11nm, 10nm, 8nm - FFC, FFPGL, FF |