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Overview
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR4, LPDDR3, DDR4, DDR3, and/or DDR3L SDRAM interfaces operating at up to 4,267 Mbps.
With multiple interfaces, the LPDDR4 multiPHY can, for example, be used in a mobile application such as a smartphone that requires high-performance LPDDR4 mobile SDRAM support and also used in a larger form factor budget tablet application requiring DDR4 or DDR3 SDRAMs.
With multiple interfaces, the LPDDR4 multiPHY can, for example, be used in a mobile application such as a smartphone that requires high-performance LPDDR4 mobile SDRAM support and also used in a larger form factor budget tablet application requiring DDR4 or DDR3 SDRAMs.
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Tech Specs
| Part Number | dwc_lpddr4_multiphy_v2_tsmc |
| Short Description | LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm) |
| Provider | |
| Maturity | Available on request |
| Foundry | TSMC |
| Geometry nm | 12, 16, 22, 28 |
| Target Process Node | TSMC 28nm, 22nm, 16nm, 12nm - HPC+, ULP, FFC |