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Overview
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY’s cost-effective solution meets the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
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Tech Specs
Part Number | dwc_pcie4phy_tsmc |
Short Description | PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P) |
Provider | |
Foundry | TSMC |
Geometry nm | 3, 7, 12, 16, 28 |
Target Process Node | TSMC 28nm, 16nm, 12nm, N7, N3P - HPC+, FFPGL, FFC, FF, PFF |