Interface Controller & PHY
 AMBA AHB / APB/ AXI (57)
 CXL (12)
 Gen-Z (6)
 HDMI (48)
 I2C (52)
 Interlaken (2)
 MIL-STD-1553 (2)
 MIPI (302)
 Multi-Protocol PHY (44)
 PCI (124)
 RapidIO (19)
 SAS (8)
 SATA (81)
 Smart Card (6)
 USB (301)
 V-by-One (17)
 VESA (71)
 Other (72)
Search Silicon IP  
Foundry
 AMS  CSMC  Dongbu
 Fujitsu  GlobalFoundries  GSMC
 HHGrace  IBM  IDM
 LFoundry  MXIC  POWERCHIP
 Samsung  Silterra  SMIC
 STMicroelectronics  TowerJazz  TPSCo
 TSMC  UMC  VIS
 XFAB
Geometry
 2 nm  3 nm  4 nm  5 nm  6 nm  7 nm
 8 nm  10 nm  11 nm  12 nm  13 nm  14 nm
 15 nm  16 nm  18 nm  20 nm  22 nm  25 nm
 28 nm  35 nm  40 nm  45 nm  54 nm  55 nm
 63 nm  65 nm  80 nm  85 nm  90 nm  95 nm
 108 nm  110 nm  130 nm  135 nm  140 nm  150 nm
 152 nm  153 nm  160 nm  180 nm  220 nm  250 nm
 280 nm  300 nm  350 nm  400 nm  450 nm  500 nm
 1340 nm  1370 nm
OK
124 Silicon IP

1
PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
PCIe 5.0 Controller

2
PCIe 5.0 Customizable Embedded Multi-port Switch
PCIe 5.0 Multi-port Switch

3
PCIe 6.1 Controller
PCIe 6.1 Controller

4
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
PCIe 4.0 Serdes PHY IP in 12FFC

5
PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
PCIe 4.0 Controller

6
PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
XpressPCS

7
PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)
dwc_pcie4phy_tsmc

8
PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N3E, N3P)
dwc_pcie5phy_tsmc

9
PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
PCIe 2.1 Controller

10
Configurable CCIX controllers for CCIX 25G supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
dwc_ccix_25g_prem_contoller

11
Configurable controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
dwc_pci_express_1_2_controller

12
Configurable controllers for PCIe 3.1 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
dwc_pci_express_3_controller

13
Configurable controllers for PCIe 4.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
dwc_pci_express_4_controller

14
Configurable controllers for PCIe 5.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
dwc_pci_express_5_controller

15
Controllers for CCIX 25G supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications targeting automotive
dwc_ccix_25g_prem_controller_automotive

16
PCIe 2.0 PHY in Fujitsu (40nm)
dwc_pcie2phy_fujitsu

17
PCIe 2.0 PHY in SMIC (40nm, 28nm)
dwc_pcie2phy_smic

18
PCIe 2.0 PHY in TSMC (28nm, 16nm, 12nm)
dwc_pcie2phy_tsmc

19
PCIe 2.0 PHY in UMC (40nm, 28nm)
dwc_pcie2phy_umc

20
PCIe 3.0 PHY in UMC (28nm)
dwc_pcie3phy_umc

21
PCIe 4.0 PHY in
dwc_pcie4phy_samsung

22
PCIe Controller for USB4 Hosts and Devices, supporting PCIe Tunneling
PCIe Controller for USB4

23
CCIX 1.1 Controller
CCIX 1.1 Controller

24
PCI Express (PCIe) 2.1 Controller
PCI Express (PCIe) 2.1 Controller

25
PCI Express (PCIe) 3.1 Controller
PCI Express (PCIe) 3.1 Controller

26
PCI Express (PCIe) 4.0 Controller
PCI Express (PCIe) 4.0 Controller

27
PCI Express (PCIe) 5.0 Controller
PCI Express (PCIe) 5.0 Controller

28
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP/ULL
PCIe 2.0 Serdes PHY IP in 22ULP/ULL

29
PCIe 4/3/2 SerDes PHY - GLOBALFOUNDRIES 12nm
PCIe 4/3/2 SerDes PHY - GLOBALFOUNDRIES 12nm

30
PCIe 4/3/2 SerDes PHY - GLOBALFOUNDRIES 22nm
PCIe 4/3/2 SerDes PHY - GLOBALFOUNDRIES 22nm

31
PCIe 4/3/2 SerDes PHY - Samsung 14nm
PCIe 4/3/2 SerDes PHY - Samsung 14nm

32
PHY for PCIe 5.0 and CXL for TSMC 5nm FinFet
PHY for PCIe 5.0 and CXL for TSMC 5nm FinFet

33
PHY for PCIe 5.0 and CXL for TSMC 7nm FinFet
PHY for PCIe 5.0 and CXL for TSMC 7nm FinFet

34
PHY for PCIe 6.0 and CXL for Samsung SF5A
PHY for PCIe 6.0 and CXL for Samsung SF5A

35
PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet
PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet

36
PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
PCIe 2.0 Serdes PHY IP in 28HPC

37
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
PCIe 3.0 Serdes PHY IP in 22ULP

38
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
PCIe 2.0 Serdes PHY IP in 28HPCP

39
12G Multiprotocol Serdes IP, Silicon Proven in SMIC 14SF+
12G Multiprotocol Serdes IP in 14SFP

40
PCIe 1.1 Controller with PHY Interface for PCI Express (PIPE) specification and native user interface support
PCIe 1.1 Controller

 | 
 Previous Page
 |  1 | 2 | 3 | 4 | 
Next Page 
 | 

 Back


I understand
This website uses cookies to store information on your computer/device. By continuing to use our site, you consent to our cookies. Please see our Privacy Policy to learn more about how we use cookies and how to change your settings if you do not want cookies on your computer/device.