|
Overview
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE 4.4 interface spec. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since a fore mentioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.
Please sign in to view full IP description :
Tech Specs
Part Number | PCIe 4.0 Serdes PHY IP in 12FFC |
Short Description | PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC |
Provider | |
Maturity | In Production |
Foundry | TSMC |
Geometry nm | 12 |
Target Process Node | TSMC 12FFC |