|
|
Overview
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s
applications’ demands for higher bandwidth. The PHY’s cost-effective solution meets the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
applications’ demands for higher bandwidth. The PHY’s cost-effective solution meets the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Please sign in to view full IP description :
Tech Specs
| Part Number | dwc_pcie5phy_tsmc |
| Short Description | PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N3E, N3P) |
| Provider | |
| Foundry | TSMC |
| Geometry nm | 3, 5, 6, 7, 12, 16 |
| Target Process Node | TSMC 16nm, 12nm, N7, N6, N5, N3E, N3P - FFC, FF, EFF, PFF |