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Overview
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for embedded mass-storage flash memory (eMMC) and removable flash memory card (SD Card), targeting a range of applications. The Synopsys SD/eMMC PHY IP, compliant with the latest JEDEC and SD specifications, is a fully integrated hard macro with high-speed IOs and Delay Locked Loop (DLL)/delay lines. Optimized for power and area, the PHY IP is fully verified and configurable for easy integration into application processors. The PHY IP and Synopsys SD/eMMC Host Controller IP offer a fully verified solution that designers can use to integrate the latest embedded and removable memory functionality into their application processor, while speeding time-to-market.
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Tech Specs
Part Number | dwc_sd_emmc_tsmc |
Short Description | SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6) |
Provider | |
Maturity | Available on request |
Foundry | TSMC |
Geometry nm | 6, 7, 12, 16, 28 |
Target Process Node | TSMC 28nm, 16nm, 12nm, N7, N6 - HPCP, HPM, FFPGL, FFPL, FFC, FF |