Duet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)

Overview

The Synopsys Duet Packages of Embedded Memories and Logic Libraries, part of Synopsys Foundation IP portfolio, offer an integrated portfolio of standard cell libraries, memory compilers and memory test and repair capability. The optimized combinations of high-performance and high-density SRAMs, register files, ROMs, standard cells, and Power Optimization Kits (POKs) provide all the elements needed to implement a complete system-on-chip (SoC). Options for overdrive/low voltage, process, voltage, temperature corners (PVTs), high-density SRAMs and multi-channel logic standard cells are also available, enabling designers to achieve the highest quality of results for their SoC in their specific application.

Tech Specs

Part Numberdwc_duet_embedded memories_logic libraries_huali
Short DescriptionDuet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)
Provider
Maturity Available on request
Geometry nm40, 55
Target Process NodeHuali 55nm, 40nm - LP
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