Memory & Logic Library
 Embedded Memories (1862)
 I/O Library (635)
 Standard cell (637)
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Foundry
 AMS  CSMC  Dongbu
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 HHGrace  IBM  IDM
 LFoundry  MXIC  POWERCHIP
 Samsung  Silterra  SMIC
 STMicroelectronics  TowerJazz  TPSCo
 TSMC  UMC  VIS
 XFAB
Geometry
 2 nm  3 nm  4 nm  5 nm  6 nm  7 nm
 8 nm  10 nm  11 nm  12 nm  13 nm  14 nm
 15 nm  16 nm  18 nm  20 nm  22 nm  25 nm
 28 nm  35 nm  40 nm  45 nm  54 nm  55 nm
 63 nm  65 nm  80 nm  85 nm  90 nm  95 nm
 108 nm  110 nm  130 nm  135 nm  140 nm  150 nm
 152 nm  153 nm  160 nm  180 nm  220 nm  250 nm
 280 nm  300 nm  350 nm  400 nm  450 nm  500 nm
 1340 nm  1370 nm
OK
3134 Silicon IP

1
High-Density eMRAM Compiler TSMC 22ULL
dwc_comp_ts22nlh41p11saemr128s

2
Duet Package of Embedded Memories and Logic Libraries for GF (55nm, 40nm, 22nm)
dwc_duet_embedded memories_logic libraries_gf

3
Duet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)
dwc_duet_embedded memories_logic libraries_huali

4
Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)
dwc_duet_embedded memories_logic libraries_smic

5
Duet Package of Embedded Memories and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4P)
dwc_duet_embedded memories_logic libraries_tsmc

6
Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)
dwc_duet_embedded memories_logic libraries_umc

7
NVM FTP Trim in SMIC (180nm, 110nm)
dwc_nvm_ftp_trim_smic

8
NVM FTP Trim in TowerJazz (180nm)
dwc_nvm_ftp_trim_towerjazz

9
NVM FTP Trim in TSMC (180nm, 152nm, 150nm, 130nm)
dwc_nvm_ftp_trim_tsmc

10
NVM MTP in Silterra (180nm)
dwc_nvm_mtp_silterra

11
NVM MTP in TSMC (180nm, 152nm, 65nm, 55nm, 40nm)
dwc_nvm_mtp_tsmc

12
NVM OTP in Dongbu (180nm, 150nm, 110nm)
dwc_nvm_otp_dongbu

13
NVM OTP in Fujitsu (90nm, 65nm, 55nm, 40nm)
dwc_nvm_otp_fujitsu

14
NVM OTP in SMIC (110nm, 65nm, 55nm, 40nm)
dwc_nvm_otp_smic

15
NVM OTP in TSMC (180nm, 152nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm, 28nm, 22nm, 16nm, 12nm, N7, N6, N5, N4P)
dwc_nvm_otp_tsmc

16
NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
dwc_nvm_otp_umc

17
LVDS Rx IP, Silicon Proven in GF 28LPe
LVDS Rx IP in 28SLP

18
LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL
MIPI D-PHY/LVDS Tx Combo PHY IP

19
LVDS/FPD Link IP, Silicon Proven in GF 28LPe
LVDS/FPD Link IP in 28SLP

20
LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
LVDS/FPD Link IP in 65/55LPe

21
V-by-One Tx IP, Silicon Proven in SMIC 40LL
V-by-One Tx IP in 40LL

22
12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
SESAME-BiV_TSMC_40nm_LPeF

23
12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
SESAME-BiV_TSMC_40nm_LP

24
12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
SESAME-BiV_TSMC_40nm_uLP

25
12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
SESAME-BiV_TSMC_40nm_uLPeF

26
6 track Ultra High Density standard cell library at TSMC 55 nm
SESAME-uHD-BTF_TSMC_55nm_eFlash_SVT

27
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V)
SESAME-eLC-DV_TSMC_180nm_G_SVT

28
9 track standard cell library at TSMC 55 nm
SESAME-9T-DV_TSMC_55nm_uLP-eF_SVT

29
9 track standard cell library at TSMC 55 nm
SESAME-9T-DV_TSMC_55nm_uLP_SVT

30
CLICK - The universal solution of power gating for the whole SoC
SESAME-CLICK_TSMC_22nm_ULL_EHVT

31
CLICK - The universal solution of power gating for the whole SoC
SESAME-CLICK_TSMC_22nm_ULL_SVT

32
CLICK - The universal solution of power gating for the whole SoC
SESAME-CLICK_TSMC_40nm_uLP_HVT

33
CLICK - The universal solution of power gating for the whole SoC
SESAME-CLICK_TSMC_40nm_uLPeF_HVT

34
Dual Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 80 k
DpRAM-ERIS-NV-HD-RR.b-HVT.HVT_TSMC_90nm_eF_Generator

35
Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
DpRAM-ERA-DR-HD-RR-ERS_b-LP-SVT_SVT_TSMC_40nm_ULP

36
Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
DpRAM-ERA-DV-HD-RR.b-eHVT.SVT-HVT_TSMC_55nm_ULP

37
Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
DpRAM-ERA-DV-HD-RR.b-eHVT.SVT-HVT_TSMC_55nm_ULP-eF

38
Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
DpRAM-ERA-M1-DV-HD-RR.b-eHVT.SVT-HVT_TSMC_55nm_ULP-eF

39
Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
sROMet-PHOENIX-uHDeLL_TSMC_90nm_LP_Generator

40
Metal programmable ROM compiler - Memory optimized for low power and high density - compiler range up to 1024 k
dROMet-CASSIOPEIA_TSMC_152nm_LP_Generator

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