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Overview
A physical layer IP for LVDS Receiver. This IP consists of 20-lane (4 x 4D1C) LVDS receivers and supports up to 1.5Gbps data rate. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
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Tech Specs
Part Number | LVDS Rx IP in 28SLP |
Short Description | LVDS Rx IP, Silicon Proven in GF 28LPe |
Provider | |
Maturity | In Production |
Foundry | FDSOI, STMicroelectronics, GlobalFoundries |
Geometry nm | 28 |
Target Process Node | STMicro 28FDSOI |