A transmitter for LVDS with a physical layer IP. This IP has 20 lanes (4 x 4D1C) of LVDS drivers and can handle 1.5Gbps of data rate. Both serial and parallel data are divided into 4 channels in LVDS mode. Each channel of the parallel data has a width of 7 bits. There is a 25MHz to 150MHz input clock. The serializer is completely internal and doesn't need any extra parts. The circuit is modularly constructed and desensitized to handle changes. This makes process migration easier and produces a solid design