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ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)

Overview

ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash controller IP. MDLL sets the delay time for the control signal of PHY to access to the data in flash during the suitable period. Please refer to the following diagram for an overview of ONFI PHY

Tech Specs

Part NumberONFI 4.1 PHY IP
Short DescriptionONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
Provider
Maturity In Production
FoundryTSMC
Geometry nm12
Target Process NodeTSMC 12FFC
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