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You are here : Memory Controller & PHY > NAND Flash > NAND Flash Controller

ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)

Overview

ONFI PHY block is used to either transmit signal and data to NAND Flash interface, or receive the data from NAND Flash by Flash controller IP. MDLL sets the delay time for the control signal of PHY to access to the data in flash during the suitable period. Please refer to the following diagram for an overview of ONFI PHY.

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Tech Specs

Part Number	ONFi 4.0 PHY IP
Short Description	ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
Provider
Maturity	In Production
Foundry	TSMC
Geometry nm	28
Target Process Node	TSMC 28HPC+