Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard. Arasan’s ONFI 5.0 PHY IP is designed to connect seamlessly with their ONFI 5.0 Host Controller IP. Arasan’s ONFI 5.0 PHY has complete SDR, NV-DDR, NV-DDR2, NV-DDR3 and NV-LPDDR4 TX/RX functionality and supports all the speeds defined in the ONFI specification while remaining backwards compatible with the prior versions of the ONFI specifications. Arasan ONFI 5.0 PHY enables data training, various power drives and ZQ calibration, which ensures maximum operating speed and optimum signal integrity. The PHY uses a PLL / DLL combination to provide very flexible frequency access. The PHY also includes ESD protection on all the various ONFI interface pins. The Arasan’s ONFI 5.0 PHY is an area efficient with a low power consumption and the IO library supports all the features mentioned in the ONFI 5.0 specifications.