The Graphics Double Data Rate Gen6 (GDDR6) PHY is fully compliant to the JEDEC GDDR6 standard and optimized for systems that require a low-latency and high-bandwidth memory solution. The GDDR6 interface supports 2 channels, each with 16 bits for a total data width of 32 bits. With speeds up to 24 Gb/s per pin, the Cadence GDDR6 PHY offers a maximum bandwidth of up to 96 GB/s. The Cadence engineering and support teams use a system-aware design methodology for all our IP Cores to provide design flexibility and easy-to-integrate solutions. We provide full system signal and power integrity analysis to optimize performance and chip layout. In the end, the customer receives a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.