When : December 2nd-3rd, 2025
Where: Hôtel EUROPOLE
29 rue Pierre-Sémard
Grenoble, France
Join D&R IP SoC EU 25 !! A worldwide connected Event !!
A worldwide connected Event !!
IP-SoC 2025 will be the 28th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems.
The event is the annual opportunity for IP providers and IP consumers to share information about technology trends, innovative IP SoC products, Breaking IP/SoC News, Market evolution and more.
The Grenoble event is a special event as it is also the annual IP Think Tank meeting where high level executives, market analyzer and technical experts from Foundry/technology, to new applications share their vision about the future of the IP concept. It will be the right time to analyze the fast evolution and consolidation in the IP market and IP business.
As far as the application domains are concerned it is important to give high to new application domains and take into account new system requirements such as 3D packaging, Security, Artificial Intelligence, Green Electronics...
And over all you cannot miss The wine Tasting Party !!
Exhibition tables and "discussion panels" will favor vendor and customer meetings.
Any question? Please contact us
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To join the event, you need to be registered.
If not yet done, Register Now !
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9.00 am
Keynote Session
Chairperson: Gabrièle Saucier - Design And Reuse
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Welcome to the IP-SoC Community
Gabrièle Saucier
CEO
Design And Reuse
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When the Silicon Becomes the First Line of Cyber Defense
Philippe Flatresse
Soitec
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Systolic array architectures for space and defense applications
Constantin Papadas
ISD
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with Tim Helfers
Airbus D&S
and R. Wiest
Airbus D&S
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Break
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10.20 am
Processor IP
Chairperson: Srinivasa Raghavan Parthasarathy - HCLTech
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Equivalence checking: proving correctness of RISC-V implementations when model checking cannot scale
Model checking is an exhaustive state exploration approach that guarantees a property holds. While fully automated, it often suffers from state-space explosion when applied to large industrial circuits or complex specifications. In this presen tation, we demonstrate how the exhaustive verification of a RISC-V ISA can be achieved by unlocking verification capabilities when traditional model checking alone cannot succeed.  ... 
Jonathan Certes
Formal Verification Expert
Keysom
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Building Trust from Edge to Cloud: Synopsys ARC-V Processor IP and the RISC-V Security Advantage
Ruud Derwig
Synopsys, Inc.
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Break
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11.20 am
Artificial Intelligence
Chairperson: Srinivasa Raghavan Parthasarathy - HCLTech
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Unlocking Generative AI at the Edge: How LPDDR enables Scalable & Efficient Intelligence
As generative AI continues to redefine the boundaries of creativity and automation, its true value is realized when inference is optimized for real-world deployment—especially at the edge. This presentation explores how inference serves as the c ritical enabler for delivering generative AI experiences that are responsive, efficient, and scalable. We will examine how LPDDR memory technologies, with their unique balance of high bandwidth, low latency, and cost efficiency, are ideally suited for edge AI applications—from smart cameras and industrial sensors to autonomous systems. The session will highlight architectural considerations, performance benchmarks, and deployment case studies that demonstrate how LPDDR empowers edge inference chips to meet the demands of generative AI workloads. ...
Sebastien Person
SPE Field Applications Engineering
Rambus, Inc.
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The Compiler-Free Revolution: Model-Specific ASICs as the Definitive Architecture for Sub-1W Edge AI Accelerators
DeepMentor introduces a comprehensive AI-enhanced IC design platform addressing the urgent need for efficient edge AI chip development in the growing semiconductor ecosystem. Traditional design approaches struggle with the complexity and time-to-mark et pressures of modern AI chips. Our solution integrates three core technologies: AI model miniaturization for resource-constrained deployment, automated code generation with HLS for 50%-70% faster design cycles, and intelligent architecture optimization tailored to specific AI algorithms. Validated through successful deployments in CNN and LLM chip development with various partners, our methodology reduces memory bandwidth requirements substantially while maintaining model accuracy. This white paper demonstrates how companies can leverage our approach to achieve technological sovereignty in edge AI chip design, supporting applications in automotive, industrial IoT, and smart sensing systems critical to Europe's digital transformation goals. ...
Richard Wu
General Manager
DeepMentor USA
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Sub-mW always-on Edge Neural processor with near-memory computing
Thomas Gillot
AI Business Developer
Asygn
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Lunch Break
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1.00 pm
Security (1)
Chairperson: Graham Woods - Synopsys
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Hardware-Rooted Security - How to Protect Already-Deployed Devices against Reverse Engineering & Firmware Cloning
Ruud Derwig
Synopsys, Inc.
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with Marc Fyrbiak
Emproof
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Designing Single- and Multi-Mode Post-Quantum Cryptography IP Cores: Architectural Challenges and Integration Strategies
As PQC standards mature, SoCs must support multiple algorithms such as ML-KEM and ML-DSA efficiently. This talk explores design strategies for single- and multi-mode PQC IPs, covering architecture options, shared blocks, and design alternatives balan cing flexibility, area, and performance. ...
George Athanasiou
Product Manager, Security
CAST
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Protecting Data in Motion with MACsec
As companies adopt high-performance computing, AI workloads, and cloud-edge architectures, protecting data in motion within and across networks is a growing imperative. This presentation will examine a critical technology that addresses this challeng e: MACsec (Media Access Control Security). The presentation will explore how MACsec secures Layer 2 Ethernet communications against eavesdropping, replay, and man-in-the-middle threats. In addition, given how Ethernet technology continues to scale and proliferate across the application space, current and future implementations of MACsec from the data center to the automotive market will be discussed. ...
Sebastien Person
SPE Field Applications Engineering
Rambus, Inc.
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Break
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2.20 pm
Security (2)
Chairperson: Graham Woods - Synopsys
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From Firmware to Cloud: Building PQC-Consistent Security Architectures
As quantum computing rapidly evolves, the transition to Post-Quantum Cryptography (PQC) has become a strategic priority rather than a distant concern. Following the CNSA 2.0 roadmap, PQC algorithms are being adopted for firmware and software signatur es, with full migration expected by 2030. In this talk, we will share Secure-IC’s hands-on experience integrating PQC into embedded and provisioning environments. Our experiments reveal a key insight: PQC adoption must be consistent across the entire chain— PQC consistency means that all security must be thought about throughout the product life cycle from provisioning, then in mission for all security services, until decommissioning in order to avoid any vulnerability to quantum attack. We will also explore how hybridization, backward compatibility, and future-proof architectures can be implemented effectively in iSE and Crypto Solutions. Finally, we present a “PQC-consistent” security architecture from chip to cloud designed to ensure resilience and compliance with NIST and CMVP guidelines. Join us to discover how Secure-IC is helping the industry build quantum-resilient hardware security for the next decade. ...
Léo BELLALI
Junior Field Application Engineer
Secure-IC
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Post-quantum Algorithms MS-KEM and MS-DSA Protected Against Physical Attacks, in Hardware and in Software
Post-quantum algorithms ML-KEM and ML-DSA, based on Crystals Kyber and Crystals Dilithium, respectively, have been recently standardized by NIST in FIPS 203 and FIPS 204, and are rapidly adopted worldwide. Unfortunately, these algorithms are extremel y prone to side-channel attacks, including side-channel attacks that require only one trace. Masking-based approaches to their security have a significant cost in performance, gate count, and power consumption. In addition, many practical attacks on these masking-based protected implementations have been published in academic papers. FortifyIQ has developed a unique algorithmic protection against physical attacks for both ML-KEM and ML-DSA, which is not based on masking and has a significantly better PPA than masking-based protections. It switches the calculations into a large redundant domain, following the same design principles as FortifyIQ's AES protection schemes, which have passed AVA.VAN.5 evaluation by a leading Common Criteria lab, and are deployed in millions of devices. The protection extends to operations such as composition and decomposition, which are known to be easy targets for side-channel attacks. FortifyIQ offers a combined hardware + firmware solution. For already produced devices or when limitations are preventing the use of this solution, FortifyIQ offers software libraries for both ML-KEM and ML-DSA in which the same algorithmic protection is implemented. Both products use the same unified API. ...
Yaacov Belenky
Chief Innovation Officer
FortifyIQ, Inc.
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Why anti-tamper sensors matter
Chris Morrison
Agile Analog
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Post-Quantum Cryptography: Urgent Action Required by Chip Makers
Lamyae Lahlou
Product Line Manager Security IP
Kudelski Labs
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Break
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4.00 pm
Automotive
Chairperson: Philippe Flatresse - Soitec
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Automated Generation of Automotive Grade PMU
Increasing SoC complexity involves a growing number of power domains and modes that dramatically complexify the design of Power Management Units (PMU). The flexibility of software-based PMUs accommodates such complexity at the cost of prohibitive ove rconsumptions. On the other hand, hardware-based PMUs address the energy-efficiency challenge, but their inherent lack of flexibility significantly increases the design efforts and risks. Dolphin Semiconductor's unique solution, PowerStudio & Maestro, combines the best of both worlds to reach unmatched results: Maestro is a user-configurable, low gate-count power controller (RTL IP); PowerStudio is a software tool suite to configure, integrate and test Maestro within the SoC power network. This disruptive approach shrinks PMU design efforts while achieving automotive grade reliability, marking the end of a technological antagonism. ...
Vincent Telandro
Product Marketing Manager
Dolphin Semiconductor
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4.20 pm
Video
Chairperson: Philippe Flatresse - Soitec
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JPEG XS TDC: Enabling Pristine Wireless Video with Ultra-Low Latency and Minimal Power
IntoPIX presents its JPEG XS TDC profile implementation for wireless video transmission. Delivering pristine visually lossless quality with ultra-low latency, the solution enables adaptive bitrate control and robust error concealment for unreliable w ireless channels while maintaining minimal silicon footprint and power consumption. ...
Catherine Stroobants
Market Lead for Prosumer and Consumer Electronics Solutions
intoPIX
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WhisperExtractor: When Every Mic Becomes Intelligent
WhisperExtractor (aMFCC) is Dolphin Semiconductor's groundbreaking IP that extracts Mel-Frequency Cepstral Coefficients (MFCC) directly from an analog microphone at just a few microwatts. By replacing conventional DSP-based word recognition with efficient analog-front end, it cuts energy use by ~99% and enables always-on event and voice detection in embedded devices. Come see the future of edge intelligence! ...
Etienne Faucher
Product Marketing Manager
Dolphin Semiconductor
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with Constant Essey
Analog IC Design Engineer
Dolphin Semiconductor
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Break
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5.20 pm
SOC Design platform
Chairperson: Philippe Flatresse - Soitec
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Electrical verification - The invisible bottleneck in IC design
Jean-Pierre Goujon
Customer Success Manager
Aniah
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From Standards to Silicon: Enabling the Post-Quantum Transition in SoC Design
The transition to post-quantum cryptography (PQC) is reshaping SoC design. Standards and regulations are accelerating adoption, while designers face challenges in security, certification, footprint, and crypto agility. This talk explores the roadmap and concrete use cases such as secure boot and remote attestation. # Long Version The standardization of post-quantum cryptography (PQC) by NIST and the regulatory deadlines emerging in the US, and EU are accelerating one of the most disruptive security transitions for the semiconductor industry. For SoC designers, this shift raises a set of critical challenges: ensuring robust security against side-channel and fault injection attacks, achieving compliance with certification frameworks such as FIPS, Common Criteria, and SESIP, and managing the increased memory footprint, area, and power requirements of PQC algorithms. Added to this is the demand for interoperability and crypto agility, as PQC must coexist with traditional cryptography during the transition. This talk will provide a practical roadmap, starting from standards and regulatory milestones, and moving to the specific implications for SoC and embedded platforms. A concrete use case - secure boot and remote attestation - will illustrate the integration journey. We will also present PQShield’s solutions, including PQMicroLib (lightweight PQC for constrained SoCs), its SCA-hardened implementations, and PQTrustsys, designed to bridge the gap between algorithmic innovation and silicon-ready deployment. By the end of the session, participants will leave with a clear view of both the urgency and the solutions available to make their applications, firmware and SoCs post-quantum ready. ...
Michele Sartori
Senior Product Manager
PQShield
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Break
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6.20 pm
Invited Talk
Chairperson: Gabrièle Saucier - Design And Reuse
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Forks in the Fab Five Key drivers that can potentially change the competitive stack
Title: Forks in the Fab Five Key drivers that can potentially change the competitive stack in Semi-Conductor Equipment Space (2026-2031). With the advent of accelerated tool maturity driven by AI, externalities that drive the business decisions, the decision terrain is fairly complex. While the number of factors is numerous, this presentation looks in to the critical drivers that have disproportionate impact on business. Since the Semi Equipment domain sits atop of manufacturing the Semiconductors, the upstream decisions have an impact on Semiconductor manufacturing. They have an impact on how Fab could potentially function in future (various scenarios) from the stand point of Fab Flows, Critical Bottle necks and Fab changes needed. 1. Performance headroom: e.g : Physics runway vs. incumbent 2. Adoption Friction: e.g: FAB Fit. 3. Cost-of-Ownership curve: e.g: $/ wafershift 4. Ecosystem readiness : Material Availability 5. Externalities : ESG / Export controls etc The presentation would deal with potential scenarios that can play out. ...
P.SRINIVASA RAGHAVAN
Practice Head - Semiconductor BU
HCLTech
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9.00 am
Keynote Session
Chairperson: Gabrièle Saucier - Design And Reuse
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Advancing AI with game-changing photonics substrates
Yannick Larvor
Business Development Manager
Soitec
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9.20 am
European policies
Chairperson: Gabrièle Saucier - Design And Reuse
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European policies on Semiconductors : from Chips Act1 to Chips Act 2.0
Dominique THOMAS
STMicroelectronics
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Meet IC-DASH, The French Design Enablement Team of the European Chip Design Platform
Alexandre Valentian
CEA
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Explore unparalleled Opportunities with Europe's Advanced Design Enablement Team
Patrick Döll
Head of Design Enablement
Racyics GmbH
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Break
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10.40 am
Design Platform
Chairperson: Dominique Thomas - STMicroelectronics
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Network-on-Chip (NoC) automation simplifies reuse in derivative System-on-Chip (SoC) design
Many System-on-Chip (SoC) designs are derivatives, but the changes required to the Network-on-chip (NoC) to accommodate IP modifications significantly complicates RTL and layout reuse. We will show how smart NoC IP with full and incremental automatio n capability simplifies derivative SoC design, reducing time to market and delivering better results. ...
Rick Bye
Director Product Management
Arteris
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A software and hardware AI platform for efficient deployment at the edge
Alexandre Valentian
CEA
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Break
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11.40 am
Power Optimization
Chairperson: Dominique Thomas - STMicroelectronics
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Enabling Advanced Power Optimization Features in FDSOI-based SoCs
The integration of advanced power optimization features such as ABB and DVFS within complex FDSOI-based systems presents notable architectural and implementation challenges. This work explores those and demonstrates how to effectively enable energy-e fficient, high-performance SoC architectures. ...
Marcus Pietzsch
Racyics GmbH
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Wideband and energy-efficient data converter solutions
InCirT will present its cutting-edge Fourier-Domain converter IP for ultra-wideband DAC/ADC (FDDAC, FDADC, FD-TRx), plus supporting blocks. The session highlights how our technology enables ultra-efficient, high-precision data conversion for next-gen eration telecom, radar, and high-performance data systems. ...
Oner Hanay
CEO
InCirT GmbH
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Redefining Clock Domain Crossing: Innovative low power architectures for next generation SoCs
Modern digital and mixed-signal System-on-Chip (SoC) designs incorporate multiple clock domains to optimize dynamic power and maximize throughput. These domains frequently exchange data and control signals, making Clock Domain Crossing (CDC) a critic al challenge. Improper handling of CDC can lead to data corruption and metastability, threatening system reliability. Conventional solutions such as FIFOs, multi-stage synchronizers, and metastability-hardened flip-flops are widely used but often introduce substantial area, power, and latency overheads, reducing the overall efficiency of the design. This contribution showcases architectural innovations aimed at minimizing power consumption in CDC circuits while maintaining robust performance. The proposed solutions focus on optimizing both data and control path interfacing across clock domains, significantly improving the figure of merit in terms of power, area, and latency. These architectures mitigate CDC logic, reduce the number of required synchronization elements, and eliminate the need for traditional reset synchronizers through timing-aware signal management. By addressing CDC challenges with low-power, high-efficiency design strategies, this work contributes to the development of scalable and energy-conscious SoC architectures. The techniques are particularly suited for applications where power and area constraints are critical, offering designers a practical path towards more efficient, sustainable integrated systems. ...
Aradhana Kumari
Staff Engineer
STMicroelectronics
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Lunch Break
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1.20 pm
Monitoring and Verification
Chairperson: Patrick Döll - Racyics GmbH
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SLM IP and Analytics
To keep pace with the ever-growing performance demands of SOCs used for cutting-edge applications like HPC and automotive, device and system complexity continues to increase. The emergence of multi-die technology has also compounded this complexity. To meet these demands, designers can optimize both the health and performance of their silicon by gathering meaningful data at each stage of the device lifecycle and from silicon to system that can provide actionable insights for intelligent decision making. Synopsys SLM Silicon.da, part of the Synopsys.ai™ EDA suite, leverages the source pre-silicon design and various post-silicon data sources – monitor IP, diagnostic, fab and production test – to improve key chip production metrics such as quality, yield, and throughput, as well as key silicon operational metrics such as chip power and performance. As part of its full breadth analytics solution, Silicon.da offers monitor-based analytics of your embedded PVT IP. Silicon Lifecycle Management (SLM) is built on a foundation of in-chip monitors IP, data analytics and design automation. Environmental, structural, and functional monitors enable these actionable insights which can be leveraged from the early In-Design phase to In-Ramp, In-Production and ultimately In-Field operation. Please join us to learn more about Synopsys SLM IP portfolio and an introduction to Silicon.da ...
Graham Woods
Synopsys, Inc.
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AI-assisted IP & SoC Verification: Making It Right
Large Language Models (LLMs) and other AI tools are rapidly making their way into our engineering workflows, including in coding assistants, IDEs, and now, within EDA tools from the “big three” vendors. This shift is changing how we work as verification engineers. But while AI brings real productivity gains, it must not come at the cost of quality. Verification is a discipline of rigor, and blindly delegating part or all of the job to AI is not just risky, it can be reckless. This presentation explores the growing role of AI in IP and SoC verification, looking at both its potential and its limitations. We’ll highlight common risks such as hallucinations, overconfidence, and reinforcement of human bias, and propose concrete principles for using AI responsibly in verification workflows, from planning to coverage closure. Through a case study focused on AXI controller verification, we’ll show how LLMs can help build, review, and improve verification plans, while remaining fully under the engineer’s control. We’ll also touch on key operational concerns like confidentiality, on-premise usage, and how to strike the right balance between automation and engineering judgment. Attendees will walk away with both a practical framework and real-world insights to start using AI as a trusted assistant, without compromising the integrity of the verification process. ...
Francois Cerisier
CEO
AEDVICES
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Liberating Functional Verification from Boolean Shackles
Vikas Sachdeva
Senior Director of Product Strategy and Business Development
Real Intent Inc.
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Break
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2.40 pm
Rule checking and eCO
Chairperson: Gabrièle Saucier - Design And Reuse
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Standardizing CDC and RDC abstract models
CDC-RDC analysis has evolved as an inevitable stage in RTL quality signoff in the last two decades. Over this period, the designs have grown exponentially to SOC’s having 2 trillion+ transistors and chiplet’s having 7+ SOC’s. Today CDC verification has become a multifaceted effort across the chips designed for clients, servers, mobile, automotives, memory, AI/ML, FPGA etc… with focus on cleaning up of thousands of clocks and constraints, integrating the SVA’s for constraints in validation environment to check for correctness, looking for power domain and DFT logic induced crossings, finally signing off with netlist CDC to unearth any glitches and corrupted synchronizers during synthesis. As the design sizes increased in every generation, the EDA tools could not handle running flatly and the only way of handling design complexity was through hierarchical CDC-RDC analysis consuming abstracts. Also, hierarchical analysis helps to enable the analysis in parallel with teams across the globe. Even with all these significant progress in capabilities of EDA tools the major bottleneck in CDC-RDC analysis of complex SOC’s and Chiplets is consuming abstracts generated by different vendor tools. Different vendor tool abstracts are seen because of multiple IP vendors, even in house teams might deliver abstracts generated with different vendors tools. The Accellera CDC Working-Group aims to define a standard CDC-RDC IP-XACT / TCL model to be portable and reusable regardless of the involved verification tool. As moving from monolithic designs to IP/SOC with IPs sourced from a small/select providers to sourcing IPs globally (to create differentiated products), the quality must be maintained as driving faster time-to-market. In areas where the standards (SystemVerilog, OVM/UVM, LP/UPF) are present, the integration is able to meet the above (quality, speed). However, in areas where standards (in this case, CDC-RDC) are not available, most options trade-off either quality, or time-to-market, or both :-( Creating a standard for inter-operable collateral addresses this gap. This presentation aims to remind the definitions of CDC-RDC Basic Concepts and constraints, as well as the description of the reference verification flow, and addressing the goals, scope, structure & deliverables of the Accellera CDC Working Group in order to elaborate a specification of the standard abstract model. A status related to the last LRM version open to public review by 2025-Q4, will be presented. ...
Jean-Christophe Brignone
SMTS
STMicroelectronics
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ECO with najaeda: Python-Based Netlist Editing with Integrated LEC
keplertech.io is an EDA startup focused on new generation solutions and the publisher of the advanced python library, najaeda, that can analyze and edit industrial grade post synthesis netlists. In this talk we will explore the library capabilities , integrated formal solution, industrial adoption for ECO and the roadmap ahead. ...
Noam Cohen
Co-Founder and CTO
keplertech.io
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