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1
Arm Allinea Studio
High Performance Tools for Developing Arm Based HPC Solutions

2
Arm SDK-700 System Design Kit
The Arm SDK-700 System Design Kit offers a solution to help build secure SoCs for rich IoT nodes, gateways, and embedded applications.

3
complete measurement subsystem IP for single phase power metering
Dolphin Design

4
Configurable SoC Platform 8051
The SOCC-1110 is an 8051 based configurable SoC platform. The platform contains an 8051 CPU core, and all the peripheral functions required for a basic SoC. The SOCC-1110 contains a single cycle 8051...

5
Cortex-A5 DesignStart Pro
The Arm Cortex-A5 processor is ideal for building high-performance and feature-rich SoCs for embedded and IoT applications. The Cortex-A5 processor is the smallest application processor in the Cortex-...

6
Fastest Power Emulator for Hardware-Software Power Verification
ZeBu® Empower delivers breakthrough performance for fast hardware-software power verification. Its performance enables multiple iterations per day with actionable power profiling in the context of...

7
I3C HDK
The I3C Total IP in a box HDK gives I3C SoC developers all the resources they need to implement MIPI I3C specifications right out of the box.

8
In-Chip Monitoring Subsystem for Process, Voltage & Temperature (PVT) Monitoring
A full suite of embedded monitoring IP managed by a PVT controller with standard interfaces, creates a complete subsystem dedicated to maximizing performance, optimizing power, reliability and enablin...

9
PVT Controller (Series 4) (Sub-system for complete PVT monitoring)
The PVT Controller provides a standard digital interface to the embedded Process, Voltage and Temperature (PVT) sensing Sub-System used to increase System on Chip performance and reliability. On-chip ...

10
SHS is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores

The DesignWare® STAR Hierarchical System is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores, including analog/ mixed-si...


11
SMS is a comprehensive, integrated test, repair and diagnostics solution
The DesignWare® Self-Test and Repair (STAR) Memory System™ is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or nonrepairable embedded memories across any f...

12
SOCC 2110 Configurable SoC Platform 80251
The SOCC-2110 is an 80251 based configurable SoC platform. The platform contains an 80251 CPU core, and all the peripheral functions required for a basic SoC. The SOCC-2110 contains a single cycle 80...

13
SPIDER - Power Management Platform
SPIDER platform is a turnkey solution to achieve advanced power network design, verification & integration in weeks instead of months.

14
VC Functional Safety Manager
VC Functional Safety Manager provides a comprehensive tool for IP and semiconductor groups targeting functional safety certification for ISO 26262, IEC 61508 and other functional safety standards. It ...

15
ZSP-USB-JTAG Emulator
The ZSP-USB-JTAG emulator probe enables efficient and productive embedded software debugging. This compact and portable probe is powered by the USB port and utilizes the JTAG interface for debugging Z...

16
ZView IDE - ZSP Development Environment
The ZView Integrated Development Environment (IDE) features a debugger as part of the Eclipse software development environment. Eclipse is an open, industry supported, extensible, software development...

17
CAN 2.0 & CAN FD Reference Design
It is a complete reference design for a CAN node subsystem based on the CAN-CTRL CAN 2.0 & CAN FD Bus Controller IP Core. It can be used for evaluating the CAN-CTRL core, and it enables the rapid development of CAN FD applications or device prototypes.

18
Codasip Studio
Codasip Studio is a complete set of Electronic Design Automation (EDA) tools for processor design and customization. The level of automation is unmatched on the market, and produces fast and efficient...

19
Customizable Power Management Platform
This silicon proven, customizable integrated power management subsystem provides a cost-effective single-chip solution for power management. Typical target applications include portable low-power consumer products or any application, with a need to control diverse power domains.

20
GUC HBM2 Controller and PHY IP
GUC HBM2 IP is a complete solution for SoC design targeting high bandwidth applications such as AI, HPC, data centers and networking.

21
GUC N5 ASIC Platform
The industry leading N5 ASIC platform aiming for High Performance Computing, AI/ML, and Networking applications, providing comprehensive N5 IP ecosystem along with advanced 2.5D package (CoWoS,InFO_oS) solution.

22
MimicPro FPGA PROTOTYPING SYSTEM
The Corigine©MimicProPrototyping System is a high-performance,FPGA-based system that raises prototyping to an unprecedented new level.

23
Proteus
A one-stop software platform which applies analytics to data created by on-chip Agents™

24
ACAP IP Framework for Multi-Camera Vision Applications

The logiREF-VDF-ACAP Video Design Framework enables Xylon logiVID-ACAP Vision Development Kit users to quickly utilize the provi...


25
Analog FastSPICE Platform

Foundry-certified, the AFS Platform delivers nm SPICE accuracy >5x faster than traditional SPICE and >2x faster than parallel SPICE simulators. Offering the world s fastest nm circuit verification ...


26
Analytics and optimization

System designers can use Tessent Embedded Analytics SoC monitoring and analytics features to refine performance based on the in-silicon behavior of their SoCs.

All too often, the real-world ...


27
Cortus Development Platform with Spartan-6 X75 FPGA with 1 Mbyte of SRAM
The Cortus Development Platform is an ideal tool for evaluating and prototyping the full range of Cortus APS 32 bit processor cores. It is also a vehicle for developing hardware and software for Cortus-based systems including multi-core ones.

28
Display port 2.0 VIP
Display port 2.0 is the serial communication protocol developed by Video Electronics Standards Association(VESA) to support the video,audio and other data between a source device and sink device. Display port 2.0 VIP can be used to verify transmitter or Receiver device following the Display port basic protocol as defined in Display port 2.0.

29
FPGA-to-ASIC Conversion Service
FPGA-to-ASIC conversion service is introduced to meet the requirements of lower BOM cost, lower power consumption, higher integration for miniaturization, and long-term supply commitments, as well as a strategic response to FPGA End-of-Life (EOL) events.

30
In-field
Use of on-chip processing allow the system manufacturer to enable development and optimization to be performed on the finished system, even after the device is shipped.

31
Intelligent Sensor and Power Management Design Platform
Integrated ASIC design platform for low power analog/mixed signal ASICs for IoT, Smart Home, Healthcare, Wearables, and Industrial applications that will simplify, streamline and reduce the cost for new ASIC designs.

32
logiVID-Z Vision Development Kit
The logiVID-Z Vision Development Kit provides system designers with everything they need to efficiently develop multi-camera vision applications on the Xilinx Zynq-7000 AP SoC. The complete hardware p...

33
Nucleus ReadyStart
The Nucleus ReadyStart platform brings together all the components required to develop devices that require hard real-time performance with a small footprint.

34
NVMe-Xactor VIP Solution
NVMe-Xactor is a comprehensive VIP solution portfolio for NVMe 1.2 used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance.

35
OpenCAPI VIP
The SmartDV s OpenCAPI Verification IP is fully compliant with OpenCAPI Specification V3.0 and V3.1 and verifies OpenCAPI interfaces.

36
SD Express Card Verification IP
Truechip's SD Express Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Express Interface of an ASIC/FPGA or SoC.

37
SimAccel FPGA-Accelerated Verification
Accelerate RTL Verification and SW Bring-up Target IPs and SoCs
  • NVMe controller
  • PCIe RC/EP IP, Repeater, Switch
  • Flash controller
  • AMBA NoCs and peripherals
  • M...

38
SimCluster GLS
Gate-Level Parallel Simulation : Reduce Time to Simulation Sign-off

39
SimXACT - Gate Simulation Productivity and Analysis Technology
Gate-Level X-Verification : Reduce Bring-up Time

40
SoC Debug
The average SoC now has more than 100 IP blocks. Such devices are powerful, but there is a problem: they are so complex that it is effectively impossible to understand how they operate in every circumstance.

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