www.design-reuse-embedded.com
133 Solutions

1
ACE software
ACE works in conjunction with industry-standard synthesis tools, allowing FPGA designers to easily map their designs into Achronix Speedster®22i FPGAs.

2
Arm Allinea Studio
High Performance Tools for Developing Arm Based HPC Solutions

3
Arm SDK-700 System Design Kit
The Arm SDK-700 System Design Kit offers a solution to help build secure SoCs for rich IoT nodes, gateways, and embedded applications.

4
Cadence Verification Suite
Applying innovative solution flows, automation tools, and best-in-class verification engines is necessary to overcome the resulting verification gap.

5
CloudBurst Platform
Built for Hybrid Environments

The majority of companies developing ICs have significant investments in computing capacity in the form of on-premises datacenters. For efficiency reasons, c...

6
Cortex-A5 DesignStart Pro
The Arm Cortex-A5 processor is ideal for building high-performance and feature-rich SoCs for embedded and IoT applications. The Cortex-A5 processor is the smallest application processor in the Cortex-...

7
Genus Synthesis Solution
Delivering the best possible productivity during RTL design and the highest quality of results (QoR) in final implementation

8
I3C HDK
The I3C Total IP in a box HDK gives I3C SoC developers all the resources they need to implement MIPI I3C specifications right out of the box.

9
Innovus Implementation System
The Cadence® Innovus™ Implementation System is optimized for industry-leading embedded processors, as well as for 16nm, 14nm, 10nm, and 7nm processes, helping you get an earlier design start with a faster ramp-up.

10
Joules RTL Power Solution
Built on a multi-threaded frame-based architecture, the Joules RTL Power Solution delivers 20X faster time-based RTL power analysis as compared to other methods.

11
Palladium Z1 Enterprise Emulation System

Verification has become the biggest challenge in SoC development. However, traditional verification tools have not kept pace with how quickly SoC and ASIC design size and complexity are growing. Si...


12
Perspec System Verifier
Frustrated by all of the manual effort and time you're spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence® Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days.

13
Protium S1 FPGA-Based Prototyping Platform
The Protium™ S1 FPGA-Based Prototyping Platform is the latest generation prototyping solution enabling early software development, throughput regressions, and high-performance system validation. It combines high-capacity FPGA boards, based on Virtex-Ultrascale FPGAs, with a complete implementation and debug software suite, providing ultra-fast design bring-up and unprecedented ease of use.

14
Protium X1 Enterprise Prototyping Platform
The Cadence® Protium™ X1 Enterprise Prototyping Platform is a first-of-its-kind enterprise prototyping platform. Architected from the ground up to provide extreme scalability and flexibility in a data center-optimized form factor, it is addressing your requirements of today, and growing with you, as your designs and demands are growing tomorrow.

15
SHS is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores

The DesignWare® STAR Hierarchical System is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores, including analog/ mixed-si...


16
SMS is a comprehensive, integrated test, repair and diagnostics solution
The DesignWare® Self-Test and Repair (STAR) Memory System™ is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or nonrepairable embedded memories across any f...

17
SPIDER - Power Management Platform
SPIDER platform is a turnkey solution to achieve advanced power network design, verification & integration in weeks instead of months.

18
VIP for DisplayPort 2.0
The Cadence® Verification IP (VIP) for DisplayPort 2.0 provides a complete bus functional model (BFM) with integrated automatic protocol checks. Incorporating the latest protocol updates, the DisplayPort 2.0 (10Gbps per lane) VIP builds on top of the mature and comprehensive VIP for DisplayPort 8K.

19
Virtuoso System Design Platform
The Virtuoso® System Design Platform links two world-class Cadence technologies–custom IC design and package/PCB design/analysis–creating a holistic methodology that automates and streamlines the design and verification flow for multi-die heterogeneous systems.

20
Xcelium Simulation on Arm-Based Servers
Verifying that system-on-chip (SoC) designs function correctly prior to manufacturing is a massive task requiring high-performance computing (HPC).

21
ZSP-USB-JTAG Emulator
The ZSP-USB-JTAG emulator probe enables efficient and productive embedded software debugging. This compact and portable probe is powered by the USB port and utilizes the JTAG interface for debugging Z...

22
ZView IDE - ZSP Development Environment
The ZView Integrated Development Environment (IDE) features a debugger as part of the Eclipse software development environment. Eclipse is an open, industry supported, extensible, software development...

23
CAN 2.0 & CAN FD Reference Design
It is a complete reference design for a CAN node subsystem based on the CAN-CTRL CAN 2.0 & CAN FD Bus Controller IP Core. It can be used for evaluating the CAN-CTRL core, and it enables the rapid development of CAN FD applications or device prototypes.

24
Connected Processor IP platform
It combines MIPS processor, Ensigma connectivity and FlowCloud platform to deliver a new class of embedded Connected Processor solutions that will power the Iernet Everywhere generation of consumer electronics.

25
Embedded PVT monitoring IP solutions
Embedded Process, Voltage and Temperature (PVT) monitoring intellectual property (IP) for advanced node System on Chip (SoC) designs for performance optimisation and statistical analysis for enhanced design enablement.

26
GUC HBM2 Controller and PHY IP
GUC HBM2 IP is a complete solution for SoC design targeting high bandwidth applications such as AI, HPC, data centers and networking.

27
GUC N5 ASIC Platform
The industry leading N5 ASIC platform aiming for High Performance Computing, AI/ML, and Networking applications, providing comprehensive N5 IP ecosystem along with advanced 2.5D package (CoWoS,InFO_oS) solution.

28
In-Chip Monitoring Subsystem Solutions
The PVT Controller is a single interface to Moortec embedded Process, Voltage and Temperature (PVT) sensing fabric. By incorporating the PVT Controller, IC developers can benefit from our extended range of compelling features.

29
MIPS Navigator Console
The Navigator Console is the command line interface software included with the Navigator EJTAG probes for debugging Imagination Technologies MIPS-based cores. Navigator Console software is based on t...

30
MIPS Navigator Probes
MIPS Navigator probes support the latest cores and licensee processors in the MIPS32 family including microAptiv, interAptiv, and proAptiv cores. It also supports the classic MIPS32 cores from the 4K ...

31
MIPS Navigator with iFlowtrace
EJTAG probe featuring iFlowtrace trace system for MIPS32, M14K, M14Kc, and M4K cores and microcontrollers. The Navigator iFlowtrace probe consists of the Navigator EJTAG probe with instruction trace ...

32
Moortec In-Chip Monitoring Subsystem on TSMC 16FFC
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices.

33
Moortec In-Chip Monitoring Subsystem on TSMC 7FF
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices. TSMC 7FF

34
Moortec In-Chip Monitoring Subsystem on TSMC N5P
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices. TSMC N5P

35
Navigator Pro Probe for MIPS 32 Cores
MIPS Navigator Pro probes support all MIPS 32 cores with PDtrace if the core is designed to stream processor trace data off-chip. Navigator Pro probes support both on-chip and off-chip trace feature...

36
PVT SubSystem
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices.

37
System Navigator Probe for 8051 Microcontroller Cores
The System Navigator probe is designed to support the special features and integrated peripherals of 8051 cores from several IP vendors. The System Navigator probes are available for the following cor...

38
Codasip Studio
Codasip Studio is a complete set of Electronic Design Automation (EDA) tools for processor design and customization. The level of automation is unmatched on the market, and produces fast and efficient...

39
FinFET-Class 7nm IP Platform
New Architectures Support High Bandwidth, High Density, Lower Power

eSilicon offers a set of high-performance and high-bandwidth IP and 2.5D solutions on 7nm technology that target...

40
FPGA-to-ASIC Conversion Service
FPGA-to-ASIC conversion service is introduced to meet the requirements of lower BOM cost, lower power consumption, higher integration for miniaturization, and long-term supply commitments, as well as a strategic response to FPGA End-of-Life (EOL) events.

 | 
 Previous Page
 | 1 | 2 | 3 | 4 | 
Next Page 
 | 
 Back

Partner with us

 

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2020 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.