What did they say at IP SoC 19 - Grenoble, France

Day 1: Executive day

8:40 am An overview on IP offer and IP demand

Gabrièle Saucier
Design & Reuse
 FDSOI Technology
Chair : Gabrièle Saucier, D&R
9:00 am Impact of the SOI technology and its European Ecosystem on the upcoming 5G technology wave

Francois Brunier
Partnership Program Manager
9:20 am Ready for flight with FD-SOI

Olivier Notebaert
On-board Data processing expert
Airbus Defence and Space
 Hot Trends
9:40 am Acceleration and Differentiation for a world of a trillion devices

Mike Eftimakis
Director of Business Innovation Strategy
10:00 am IP Status 2010-2019 – What's next for 2020-2030?

Eric Esteve
10:20 am RISC-V Helps Getting Your Chip Popular

Frankwell Lin
Andes Technology Corp.
10:40 am  Break
 IP sharing and worldwide democratization
Chair: Philippe Quinio, ST
11:00 am Integrated Circuit IP Sharing Platform - Focus on IP Services to Help Design Innovation

Weihua Xin
11:20 am Gaps and SOC consumer pain points

Mukund Pai
SoC Power Lead
Intel Corporation
11:40 am IP democratization: what are the bottleneck and the solution ?

Gabrièle Saucier
Design & Reuse
12:00 am Panel : How to improve the relations between IP consumers and IP vendors and favor IP democratizatoin?
Panel Moderator : Gabriele Saucier, D&R
Innovation leading to successful product differentiation may come from "small" IP vendors... It can be cumbersome to identify them, to get in touch with them and to assess their IP solutions.
With the participation of :
  • Mark Ma - Shanghai Jiatao Industrial Co. ltd.
  • Mukund Pai - Intel Corporation
  • Philippe Quinio - STMicroelectronics
  • Romain Tourneau - PLDA
  • Michael Lerchenmueller - Cadence
1:15 pm  Lunch Break
 Automotive and High safety systems
Chair: Olivier Notebaert, Airbus
2:15 pm Automotive-Qualified IP for Evolving Integrated ADAS Domain Controller SoCs

Ramin Navai
FAE for DesignWare Interface IP
Synopsys, Inc.
2:35 pm Autonomous Vehicle: From chip to systems design verification continuity

Gabriele Pulini
Product Marketing Manager
Mentor, a Siemens Business
2:55 pm Testability Challenge of safe-critical real-time systems

Oussama Abassi
Hardware Engineer
Safe Connect Systems
3:15 pm Data Concentrators for highly secure onboard communications systems

Vincent Laporte
3:35 pm  Break
 Security Solutions
Chair : Sakir Sezer, Titan IC
4:10 pm Why should your next secure design be PUF based

Sales Manager
Thales DIS Design Services SAS
4:30 pm FPGA-based Hardware Security Module

Pieter Willems
Director Sales and Marketing
Silex Insight
4:50 pm Secure networking in an unsafe environment

Gijs Willemse
VP, Silicon IP and Secure Protocols, Products and Engineering
5:10 pm Securing IoT with a hardware Secure Element

Marc Renaudin
Tiempo SAS
5:30 pm  Break
 Innovative solutions
Chair : Mike Eftimakis, Arm
6:00 pm A Novel Event Based Image Sensor Architecture

Mohamed Akrarai
Phd student
TIMA Laboratory
6:20 pm Embracing High Speed, Low Power, Complex Security Analytics at the Heart of the Cloud

Sakir Sezer
Titan IC
6:40 pm  Break
7:00 pm  French Wine tasting Contest
7:45 pm  Banquet

Day 2: Designer Day

 IP Ecosystem and New Standards
Chair : Alain Clouard, ST Microelectronics.
8:40 am Innovation starts here! Low-cost access to the world's best SoC portfolio

Mike Eftimakis
Director of Business Innovation Strategy at Arm
9:00 am Benefits of IP-XACT for IP Providers: Highly configurable IP study case with interconnect IP.

Vincent Thibaut
Chief Strategic Officer
9:20 am Revolutionize your products with SiFive

Christophe Wery
Sales Manager EMEA
SiFive, Inc.
9:40 am How to Identify and Minimize IP Security Risks – IP Security Assurance Standard

Ireneusz Sobanski
Senior Validation Engineer
Intel Corporation
10:00 am Panel : Is the New emerging standard IP Security Assurance (IPSA from Accelera working group) the solution?
Panel Moderator : Ireneusz Sobanski, Intel

In recent years, many hardware security weaknesses arising from integrated circuit hardware vulnerabilities have been exposed. These include lack of virtual machine isolation, secure credential leaks, and privilege escalation. These have put hardware design in the spotlight and raised questions about IC security.

  • How is security addressed over the hardware development lifecycle today?
  • How should we assess and mitigate security risk in IC design going forward?
  • Do we have adequate methodologies, procedures and technology to address it?
With the participation of :
  • Ireneusz Sobansky - Intel Corporation
  • Yann Loisel - SiFive Inc.
  • Chris Dunn - Synopsys, Inc.
  • Mark Hamption - Onespin.
11:00 am  Break
 Power Optimization
Chair : Philippe Flatresse, Dophin Design.
11:20 am Power/Performance tradeoffs and its criticality for today's SOCs

Mukund Pai
SoC Power Lead
Intel Corporation
11:40 am Simplify Energy Efficient designs with cost-effective SoC Platform

Pierre Gazull
Business Development and Marketing Manager
Dolphin Design SAS
 Analog Design and IP migration
12:00 pm Bluetooth IP Migration - Leveraging FDSOI Back Gate Biasing feature

Sowmyan Rajagopalan
Thalia Design Automation
12:20 pm Optimize the Silicon Process Porting of Physical IP

Tony Stansfield
Chief Technical Officer
sureCore, Ltd.
12:40 pm Analog Design Automation: a new approach to Analog IP

Mike Hulse
Agile Analog
1:00 pm  Lunch Break
 IP-SoC integration
Chair : Mukund Pai, Intel
1:40 pm RDC sign-off for IP integration in modern SoC designs

Johannes Biedermann
Independent Consultant
Real Intent
2:00 pm SoC Architecture: Ensuring IP Compatibilities across the SoC : Physical and Logical

Radhakrishna Moorthy Sadhu
SoC Architect, DMTS-Senior Member
Wipro Technologies
 Synchronization or asynchronous solutions
2:20 pm Desynchronizing Circuits Synthesized with CatapultC

Yoan Decoudu
PhD student
TIMA Laboratory
2:40 pm Deterministic & Precise Synchronization in sub-microsecond range using EtherFly modular IPs infrastructure

Maxime Apollonio
Digital electronic Engineer
SCS Safe Connect Systems SAS
3:00 pm  Break
 Verification & prototyping
Chair : Ahmed Jerraya, CEA LETI
3:20 pm Open Source Virtual Platforms for SW Prototyping on FPGA based HW

Mark Burton
3:40 pm Compiler Verification, More Necessary Than Ever!

Marcel Beemster
Solid Sands B.V.
4:00 pm  Conclusion and Giveaway.
Agile Analog
Dolphin Design
Real Intent
Safe Connect Systems
Solid Sands B.V.
Thalia Design Automation
Thales DIS Design Services SAS
Titan IC

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