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1
10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
The Arasan Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3- 2008 standard. The Gigabit Ethernet IP provides a 10/100 Mbps Media Independent Interface (MII) and a...

2
10G PHY for PCIe 2.0 in TSMC (7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


3
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


4
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


5
10G PHY for PCIe 3.0 in TSMC (16nm, 12nm, 10nm, 7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


6
10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications
Configurable MAC solutions for speeds from 10Gbps to 10Mbps

7
128-bit vector word length ARC VPX2 DSP IP
DesignWare® ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on devices to automotive ADAS to communications and high-performa...

8
12G PHY

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


9
12G PHY in TSMC (28nm, 16nm, 12nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


10
12G PHY in UMC (28nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


11
16G PHY

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


12
16G PHY in TSMC (28nm, 16nm, 12nm)

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


13
16G UCIe Advanced PHY for TSMC 3nm
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

14
16G UCIe Standard PHY for TSMC 3nm
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

15
16G UCIe Standard PHY for TSMC 7nm
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

16
1G to 200G High Speed Channelized Ethernet Controller MAC/PCS/FEC
200G aggregate bandwidth channelized solution for up to four Ethernet channels

17
200G/400G High Speed Ethernet Controller MAC/PCS/FEC
200G/400G bandwidth solution for one Ethernet channel

18
256-bit vector word length ARC VPX3 DSP IP
The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS applica...

19
256-bit vector word length, dual-core ARC VPX3 DSP IP with integrated hardware safety features for automotive
The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS applica...

20
25G PHY

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


21
25G PHY in TSMC (16nm, 12nm, 7nm)

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


22
32G PHY in TSMC (7nm)

The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY...


23
3DES-ECB 1 Billion trace DPA resistant cryptographic accelerator core
Rambus Crypto Accelerator 3DES-ECB Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumpti...

24
400G/800G High Speed Ethernet Controller MAC/PCS/FEC
800G/400G bandwidth solution for one Ethernet channel

25
400G/800G High Speed Ethernet Controller PCS/FEC
Up to 800G bandwidth solution for one Ethernet channel

26
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

27
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

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40G Ultralink D2D PHY for TSMC 3nm
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

29
40G Ultralink D2D PHY for TSMC 5nm
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

30
40G Ultralink D2D PHY for TSMC 7nm
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

31
512-bit dual-core vector DSP IP

The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS appl...


32
56G Ethernet PHY in TSMC (16nm, 7nm)

The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leadingedge design, analysis, simulation, and measureme...


33
6G PHY in TSMC (16nm)

The multi-lane DesignWare Multi-Protocol 6G PHY IP is part of Synopsys' highperformance multi-rate transceiver portfolio, meeting the growing needs for small area, low bill of materials (BOM) c...


34
ACS-AIP-DPHY-40GF-Auto - MIPI D-PHY in GlobalFoundries 40nm Automotive Process
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.

35
ACS-AIP-DPHY-40LP-RA - MIPI D-PHY TSMC 40LP Renesas- Automotive Grade
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.

36
AES (ECB), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
Rambus Crypto Accelerator AES-AE-Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consum...

37
AES (ECB-CBC-CFB-CTR), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
Rambus DPA Resistant AES-FBC Cryptographic Accelerator Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the powe...

38
AES CCM/GCM Engine
The EIP-39 AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O reg...

39
AES Engine
The EIP-36 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O register...

40
AES GCM/XTS Engine
The EIP-38 - AES/GCM/XTS/LRW Engines are specifically suited for next generation processors deployed in networking and storage appliances that need to support combinations of AES (with its regular fee...

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