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1
10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
The Arasan Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3- 2008 standard. The Gigabit Ethernet IP provides a 10/100 Mbps Media Independent Interface (MII) and a...

2
100 dB of SNR, 16-24-bit stereo audio CODEC with embedded regulator and cap-less headphone driver, including low-power mode
The sCODS100-LB-IO-N.15 is a feature-rich audio CODEC which provides the insurance of the best sound quality after integration into application processors for headphone.Its small area ensures a cost-e...

3
100 dB of SNR, 24-bit stereo audio CODEC with 8 ADC paths, an embedded regulator and headphone/line-out driver
The sCODa95-H1-LR_08 is a feature-rich audio CODEC which provides the insurance of the best sound quality after integration into Smart Speaker including Voice Activity Detection.It benefits from uniqu...

4
10G PHY for PCIe 2.0 in TSMC (7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


5
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


6
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


7
10G PHY for PCIe 3.0 in TSMC (16nm, 12nm, 10nm, 7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


8
128-bit vector word length ARC VPX2 DSP IP
DesignWare® ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on devices to automotive ADAS to communications and high-performa...

9
12G PHY

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


10
12G PHY in TSMC (28nm, 16nm, 12nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


11
12G PHY in UMC (28nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


12
16G PHY

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


13
16G PHY in TSMC (28nm, 16nm, 12nm)

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


14
24-bit four channel audio ADC with 95 dB Dynamic Range, compatible with Automotive requirements
The sADC-H1-LR.02 is a mixed (analog and digital) Virtual Component containing four mono ADCs, and additional functions offering an ideal mixed signal front-end for low power and high quality audio ap...

15
24-bit pure digital audio CODEC with 100 dB SNR stereo PDM-to-PCM and up to 110 dB SNR stereo PWM DAC with Automatic Gain Control and ASRC feature
The YANZI-D-sDSA-MT1.01 is a pure logic Virtual Component (ViC) containing a stereo digital microphone interface with decimation filters, an ultra dense stereo PWM DAC and additional functions offerin...

16
25-112Gbps Short-Reach PHY
The Alphawave DieCORE delivers the world’s highest density, lowest power die-to-die connectivity solution for MCMs based on IEEE XSR/USR serial standards. The DieCORE is a companion IP to the AlphaCO...

17
256-bit vector word length ARC VPX3 DSP IP
The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS applica...

18
25G PHY

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


19
25G PHY in TSMC (16nm, 12nm, 7nm)

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


20
32G PHY in TSMC (7nm)

The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY...


21
3DES-ECB 1 Billion trace DPA resistant cryptographic accelerator core
Rambus Crypto Accelerator 3DES-ECB Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumpti...

22
512-bit dual-core vector DSP IP

The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS appl...


23
56G Ethernet PHY in TSMC (16nm, 7nm)

The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leadingedge design, analysis, simulation, and measureme...


24
5G Baseband Platform IP for Mobile Broadband and IoT
PentaG2™ is CEVA’s second generation 5G NR baseband modem IP platform. It is the industry’s only platform offering capable of meeting the extreme performance, low latency and strict power budget requi...

25
5Mpixel ISP IP - 5M pixel sensor support Image Signal Processing (ISP) IP
Chips&Media s Camera ISP IP – LEDA is the Imaging Signal Processing (ISP) targeted to be used in low light environment

26
6G PHY in TSMC (16nm)

The multi-lane DesignWare Multi-Protocol 6G PHY IP is part of Synopsys' highperformance multi-rate transceiver portfolio, meeting the growing needs for small area, low bill of materials (BOM) c...


27
8K HDR display processor Vivante DC9000
High-quality and powerful display processor

28
95 dB of SNR, 16-24-bit stereo audio CODEC, with embedded regulator and differential cap-less headphone driver
Dolphin Integration s high-fidelity audio CODEC, sCODa95-H1-LR-D.04 combines a complete set of audio features and a small silicon footprint with the best resilience to noise, for the new generation of...

29
95 dB of SNR, 24-bit audio CODEC with headphone output and line-out
SoC integrators targeting portable audio applications such as Smart Phones, PMP, PDA should demonstrate optimal recording performances as well as the best sound quality, while starring the longest pla...

30
95 dB of SNR, 24-bit audio CODEC with headphone output and line-out
SoC integrators targeting portable audio applications such as Smart Phones, PMP, PDA should demonstrate optimal recording performances as well as the best sound quality, while starring the longest pla...

31
ACS-AIP-DPHY-40GF-Auto - MIPI D-PHY in GlobalFoundries 40nm Automotive Process
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.

32
ACS-AIP-DPHY-40LP-RA - MIPI D-PHY TSMC 40LP Renesas- Automotive Grade
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.

33
Active mesh against tampering attacks - Active Shield
Attacks against digital circuits can be performed by directly tampering with the device s internal structure. These attacks are intrusive, and regroup attempts to directly probe or force signals, remo...

34
Adaptive Body-Bias IP for Automotive applications, enabling Process, Voltage & Temperature compensation to leverage FDSOI forward body-biasing capabilities
* All-in-one IP including body-bias voltage generator, low power sensors and adaptive control loop * Foundation IP independent * Ultra-wide voltage range * Support of Forward Body-Biasing * Automotive...

35
AES (ECB), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
Rambus Crypto Accelerator AES-AE-Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consum...

36
AES (ECB-CBC-CFB-CTR), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
Rambus DPA Resistant AES-FBC Cryptographic Accelerator Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the powe...

37
AES CCM/GCM Engine
The EIP-39 AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O reg...

38
AES Engine
The EIP-36 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O register...

39
AES GCM/XTS Engine
The EIP-38 - AES/GCM/XTS/LRW Engines are specifically suited for next generation processors deployed in networking and storage appliances that need to support combinations of AES (with its regular fee...

40
AES Key Wrap Engine
The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and full transforms, the EP-37 accelerator provides a r...

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